dalance / sv-parser

SystemVerilog parser library fully compliant with IEEE 1800-2017
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defines and compile order #55

Closed mikrofyr closed 2 years ago

mikrofyr commented 2 years ago

Posted this question in the morty project https://github.com/zarubaf/morty/issues/39 , but probably is more related to this project. Is it possible to add support for in-order/global defines?

mydefines.sv:

// This would take presedence until undef, or new value defined by a file that is compiled later
`define DW=32

mymodule.sv

// Define from previous compiles are available, unless undef. Requires control of compilation order.
module mymodule (
 input [`DW-1:0] data
);
endmodule

morty mydefine.sv mymodule.sv

DaveMcEwan commented 2 years ago

Yes, this is already fully supported. For example, see svlint: https://github.com/dalance/svlint/blob/master/src/main.rs#L224 In particular, see the use of the mutable defines and the returned value of parse_sv() called new_defines.

mikrofyr commented 2 years ago

Thanks for clarification