Bug: Incorrect spelling of "assertion".

dalance / sv-parser

SystemVerilog parser library fully compliant with IEEE 1800-2017

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Closed DaveMcEwan closed 1 year ago

DaveMcEwan commented 1 year ago

"Asset" should be "Assert"
Applies to ImmediateAssetionStatement and DeferredImmediateAssetionItem.
Should be fixable with sed, but will require a new minor version to be released.

DaveMcEwan commented 1 year ago

I'll leave this issue open until a new release is made.