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dalance / sv-parser

SystemVerilog parser library fully compliant with IEEE 1800-2017
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Task with no direction and datatype seems to generate wrong SyntaxTree #80

Closed prokie closed 1 year ago

prokie commented 1 year ago

Hello!

Given 

task sum(a);endtask

I get the SyntaxTree

SourceText
 Description
  DescriptionPackageItem
   PackageItem
    PackageOrGenerateItemDeclaration
     TaskDeclaration
      Keyword
       Token @line:1: task
       WhiteSpace
        SpaceToken @line:1: <<<<< >>>>>
      TaskBodyDeclaration
       TaskBodyDeclarationWithPort
        TaskIdentifier
         Identifier
          SimpleIdentifier
           Token @line:1: sum
        Symbol
         Token @line:1: (
        TfPortList
         TfPortItem
          DataTypeOrImplicit
           DataType
            ClassType
             PsClassIdentifier
              ClassIdentifier
               Identifier
                SimpleIdentifier
                 Token @line:1: a
        Symbol
         Token @line:1: )
        Symbol
         Token @line:1: ;
        Keyword
         Token @line:1: endtask

But from what I can understand by reading the "Annex A Formal syntax" of IEEE 1800-2017, it should not give a PsClassIdentifier? It should be a PortIdentifier?

prokie commented 1 year ago

Just found that this is basically a duplicate of #60, so I will close this one.