Nested foreach results in parse_error

Dear Maintainers, Thanks for providing svlint (and sv-parser). The following piece of example code should be valid systemverilog from my understanding (ignore that the functionality does not make sense):

module example;
    logic [3:0][3:0][1:0] foo;
    initial begin
        std::randomize(foo);
        foreach(foo[idx]) begin
            foreach(foo[idx][jdx]) begin
                $display(foo[idx][jdx]);    
            end
        end
    end
endmodule

However, svlint reports an error in parsing this:

Error: parse error
   --> example.sv:6:19
    |
6  |           foreach(foo[idx][jdx]) begin
    |                   ^

I do not see how such a statement is invalid. Indeed, commerical tools do not complain, and simulation tools like questasim also correctly simulate this the way one would expect. I am unsure if this is an issue in svlint, or more likely in sv-parser.

The problem can circumvented by replacing the inner foreach with a normal for loop, but of course that is more verbose than necessary.

Kind regards Christian

dalance / svlint

Nested foreach results in parse_error #286