Open dignifiedquire opened 5 years ago
Do you have a Cannonlake CPU? This looks like an error that might result from specifying a target feature that your CPU doesn't support. You can check via cat /proc/cpuinfo | grep flags
.
According to proc/cpuinfo
I have
vendor_id : GenuineIntel
cpu family : 6
model : 102
model name : Intel(R) Core(TM) i3-8121U CPU @ 2.20GHz
stepping : 3
microcode : 0x2a
cpu MHz : 600.211
cache size : 4096 KB
physical id : 0
siblings : 4
core id : 1
cpu cores : 2
apicid : 3
initial apicid : 3
fpu : yes
fpu_exception : yes
cpuid level : 22
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid aperfmperf tsc_known_freq pni pclmulqdq dtes64 monitor ds_cpl vmx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch cpuid_fault epb invpcid_single pti ssbd ibrs ibpb stibp tpr_shadow vnmi flexpriority ept vpid fsgsbase tsc_adjust bmi1 avx2 smep bmi2 erms invpcid mpx avx512f avx512dq rdseed adx smap avx512ifma clflushopt intel_pt avx512cd sha_ni avx512bw avx512vl xsaveopt xsavec xgetbv1 xsaves dtherm ida arat pln pts hwp hwp_notify hwp_act_window hwp_epp hwp_pkg_req avx512vbmi umip pku ospke flush_l1d
bugs : cpu_meltdown spectre_v1 spectre_v2 spec_store_bypass l1tf
bogomips : 4416.00
clflush size : 64
cache_alignment : 64
address sizes : 39 bits physical, 48 bits virtual
If the extension doesn't exist I usually get SIGILL illegal instruction
. But this seems to be an issue with llvm not being able to lower the instructions properly.
HmmmMMMMmmmm, interesting. I'll try taking a look at this next week, but I might not have access to my Cannonlake CPU. There might be a problem because the implementation was using LLVM internals manually, since the intrinsics didn't exist when I wrote it.
Related: #256, #257 . On my cannonlake machine the current develop
branch works, but trying to remove the llvm intrinsics causes an ICE on skylake.
I was trying to test out the
avx512ifma
backend, but getting the following errorBuilding with
Rust version:
Any ideas, if this is an error on the rust compiler or the linking code being used in the backend?