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damdoy / ice40_ultraplus_examples

Examples for iCE40 UltraPlus FPGA: BRAM, SPRAM, SPI, flash, DSP and a working RISC-V implementation
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Testbench #1

Closed Deeksha-k-udayshankar closed 5 years ago

Deeksha-k-udayshankar commented 5 years ago

Do we require a testbench for the spi_hw? I tried the code with the same ice40 ultraplus board of lattice semiconductor, but my spi was not successful, just wanted to find where I am missing out. Kindly let me know about this in detail. Thanks

damdoy commented 5 years ago

Hi, What do you mean by "not successful" is it on the ice40 or the host side?

Once spi_hw example bitstream is uploaded to the ice40 board, nothing will happens, the ice40 will be stuck in the init state. It will wait for the host software located in spi_hw/spi_host/. This software will do some init on the computer side (init the ftdi lib) and send the INIT as well as other commands to the ice40 which should, among other behaviours, light up the LEDs.

Have you compiled and run the host software, does it have trouble to init the spi or to communicate with the ice40?

deekshakondiudayashankar commented 5 years ago

I am using Lattice radiant software for programming the ice40 ultra plus fpga. I wrote the top.v code and dumped that to the fpga using the radiant programmer, then went to the host side and make build and ./host but all I can receive is FxFF which is error i guess. So please let me know if I am doing it the wrong way? or I have to do any changes for it to work? Thanks

damdoy commented 5 years ago

Hi, sadly, I don't have tested most of the examples using the official Lattice software suite. The examples were synthesised and tested with the opersource suite icestorm as seen in the makefile which is included in the module. Did you also test the module with Icestorm and using the makefile, did you see the same behaviour? I'm trying to figure out the differences that could exist between the radiant software and Icestorm that could cause this problem.

deekshakondiudayashankar commented 5 years ago

I will try it with the icestorm and let you know if saw the same behaviour. Thank you

On Thu, Oct 10, 2019 at 3:09 PM Damien Doy notifications@github.com wrote:

Hi, sadly, I don't have tested most of the examples using the official Lattice software suite. The examples were synthesised and tested with the opersource suite icestorm as seen in the makefile which is included in the module. Did you also test the module with Icestorm and using the makefile, did you see the same behaviour? I'm trying to figure out the differences that could exist between the radiant software and Icestorm that could cause this problem.

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deekshakondiudayashankar commented 5 years ago

I tried it with the Icestorm and followed the same procedures. I get it as "trouble to get answer". I have attached a screenshot below, please have a look at it.

image

Thank you

damdoy commented 5 years ago

Hi, the synthesis output you show is really strange, as it states only one PLB is used, as if the top.v is empty.

Here is the result of the synthesis when I run make: statistics of yosys 0.9:

2.44. Printing statistics.

=== top ===

   Number of wires:                323
   Number of wire bits:            582
   Number of public wires:          46
   Number of public wire bits:     229
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                535
     SB_CARRY                       27
     SB_DFFE                       196
     SB_DFFSR                        1
     SB_LUT4                       310
     SB_SPI                          1

packing of arachne-pnr 0.1

After packing:
IOs          12 / 39
  IO_I3Cs    0 / 2
  IO_ODs     0 / 3
GBs          0 / 8
  GB_IOs     0 / 8
LCs          480 / 5280
  DFF        197
  CARRY      32
  CARRY, DFF 0
  DFF PASS   148
  CARRY PASS 6
BRAMs        0 / 30
WARMBOOTs    0 / 1
PLLs         0 / 1
MAC16s       0 / 8
SPRAM256KAs  0 / 4
HFOSCs       0 / 1
LFOSCs       0 / 1
RGBA_DRVs    0 / 1
LEDDA_IPs    0 / 1
I2Cs         0 / 2
SPIs         1 / 2

<timing/constraints skipped>

After placement:
PIOs       11 / 39
PLBs       124 / 660
BRAMs      0 / 30

  place time 1.37s
route...
  pass 1, 0 shared.

After routing:
span_4     633 / 23008
span_12    189 / 4464

  route time 1.35s
write_txt top.asc...
icepack top.asc top.bin

What version of yosys and arachne-pnr are you using? I used yosys 0.9 (I also tested 0.8 it works) and arachne-pnr 0.1+325+0. I made an error by forgetting to state these versions in the readme, sorry.

deekshakondiudayashankar commented 5 years ago

Yes, I got it now! My tools weren't properly installed or the version was different. Now the SPI is working as shown below and also the blue LED was glowing after programming the board. Thank you so much for your fast response and helping me with this.

image

Thanks & Regards, Deeksha

damdoy commented 5 years ago

Hi, Glad it works now. Cheers