Add Signal Save and Save All Support

[curtisma]

The Sim.Save command isn't currently implemented but is necessary to select data when simulating. Currently, I'm trying to get it to work with ngspice.

The first spot that needs to be updated: https://github.com/Vlsir/Vlsir/blob/8f866930a09309292e578559c1bb0a1ce63c919f/VlsirTools/vlsirtools/netlist/spice.py#L519

    def write_save(self, save: vsp.Save) -> None:
        txt = f".save v({save.signal})"
        return self.writeln(txt)

However self.signal is just the signal name, but actually needs to be hieratchy path to the signal. Seems this will need to be elaborated to include the hierarchy above the signal. Maybe before creation of the vlsir protocal buffer objects?

.save xtop.vbg for a top-level signal .save xtop.xdut.vbg for a signal inside the dut.

While we're add it we should include the SaveAll save mode which needs to elaborate into .save all.

[dan-fritchman]

That would be a great addition!

First-class support for this will start in Vlsir. Looking through open issues I don't see one for it.

Couple other thoughts:

• I think that to identify hierarchical signals/ instances, the information sent over Vlsir protobuf should be a list of identifiers (ie instance names), on Vlsir's terms (ie the names of the instances in the associated Vlsir modules). Different netlist formats then translate these differently. Common example: most spice-like formats (must) add the "x" subckt-instance prefix; Spectre needs not, and does not.
• In the mean time there is always one big out card as a workaround: the Hdl21/ Vlsir Literal type. That will (as it says) put its string-valued content literally & directly into any generated netlist-level output.
• The current behavior in (I think all, certainly many/ most) Vlsir simulator drivers is "save all".