FPGA integration

[BrayanBarrios]

Hi Daniel,

I was able to run LeFlow correctly and hardware was synthesized for the DE1-SoC card. That was quite interesting. Now I am trying to understand how to integrate this hardware with other types of inputs to achieve results like those of your demo. I can notice that there is a module dedicated to memory control and another dedicated to the processing of the operation, however I still can not understand how I can make it work with own data coming from other inputs.

It would be possible for you to give me a route or some suggestion to understand or achieve it, that would be very helpful for me.

Thank you very much for this tool, I have been looking for something similar and what you did is just fantastic.

[danielholanda]

Hi Brayan,

Sure, I can give you a brief explanation of how I created the demos.

There is a outer state machine that controls when things are running or not. The state of this state machine is called "y_Q". Basically I insert my inputs, change y_Q to s_Start and when y_Q becomes s_DONE I insert some new inputs and run it again.

To insert my own inputs into the design I changed the memory controller. When the design y_Q is not s_DONE, things are connected normally. Otherwise, I connect the address_a, write_enable_a and in_a to my inputs. Please note that in the example below I'm only changing the values of the inputs stored in "param1".

if (!y_Q[2]) begin
       // I didn't change anything here
    param1_address_a = memory_controller_address_a [10-1+2:2] & {10{select_param1_a}};
    param1_write_enable_a = memory_controller_write_enable_a & select_param1_a;
    param1_in_a [32-1:0] = memory_controller_in_a[32-1:0];
end

else begin
        // This is what I added
    param1_address_a = MY_INPUTS_mem_addr;
    param1_write_enable_a = MY_INPUTS_mem_wen;
    param1_in_a [31:0] = MY_INPUTS_mem_in;
end

Hope this helps