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danielholanda / LeFlow

Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks
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Documents/short-guides for hardware bridging ? #32

Closed Ruinland closed 4 years ago

Ruinland commented 4 years ago

Hi, thanks for your amazing project. I'm willing to do some research for making LeFlow to work on other FPGA platforms, i.e. Lattice ECP5. Thus end-to-end open-source FPGA toolchain (symbiflow) could be used.

Yet I'm wondering - - (1) How many LEs are used on Cyclones FPGA for the examples listed in this repo respectively ? (Hence I could evaluate whether LeFlow could fit in Lattice ECP5.) (2) What kinds of hardware IPs / peripherals provided by Altera/Board are used ? (e.g. UART/PCIe ...... etc for data exchangement ?)

Sincerely, Ruinland

danielholanda commented 4 years ago

Hi Ruinland,

Sorry for the late reply.

It is definitely interesting to make LeFlow work with Lattice devices, especially because the designs are usually quite small by default.

(1) The only numbers I have are in the paper https://arxiv.org/pdf/1807.05317.pdf (2) LeFlow works using the open version of LegUp, which has soma major limitations. One of the main limitations is the absence of peripherals. This means that all inputs and outputs are mapped to on-chip memories. In terms of IP, the only vendor-specific IP used are altfp blocks used for floating-point operations.

Hope this helps,

Daniel

On Thu, May 7, 2020 at 2:08 AM Ruinland notifications@github.com wrote:

Hi, thanks for your amazing project. I'm willing to do some research for making LeFlow to work on other FPGA platforms, i.e. Lattice ECP5. Thus end-to-end open-source FPGA toolchain (symbiflow) could be used.

Yet I'm wondering - - (1) How many LEs are used on Cyclones FPGA for the examples listed in this repo respectively ? (Hence I could evaluate whether LeFlow could fit in Lattice ECP5.) (2) What kinds of hardware IPs / peripherals provided by Altera/Board are used ? (e.g. UART/PCIe ...... etc for data exchangement ?)

Sincerely, Ruinland

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