Stereo OPL2/OPL3 playback using two SD-1 modules

[denjhang]

I've found that many OPL3 tracks have stereo, whereas the SD-1 is mono. So use two SD-1 combinations to achieve stereo.

[danielrfry]

A few people have asked about this so I'm going to try.

One potential issue is that the YMF825Board has the clock oscillator integrated. My suspicion was that the two chips running with independent clocks may produce audio signals that are out-of-phase and create unintentional stereo separation where there should be none.

As a first test, I've connected both YMF825s to the same SPI bus, sharing the same CS and RST lines, so that in theory they receive the same signals simultaneously. I recorded a sample of music playback and subtracted one channel from another in Audacity, which should result in silence if the two chips are producing the same output; however, the tracks do indeed differ in phase and some higher frequencies are still audible in the combined channels. (Those sounds are also audibly separated when listening to the unmodified output).

It's possible that running the two chips from the same clock source would solve that, however I don't have the equipment or skills necessary to remove the YMF825 (or the oscillator) from the board, nor do I have a source of bare YMF825 chips to build into a new circuit.

It's an interesting experiment nonetheless so I will try updating the code to produce stereo output, and maybe someone with the capability and resources to build a dual-YMF825 circuit can make use of it.

[denjhang]

I can build dual YMF825 modules. I am able to draw the schematic, PCB and solder, I also have some YMF825 chips enough for testing. I can assist you with hardware testing.

[danielrfry]

That would be great! I have some working code with support for stereo playback with two YMF825s (though I have some more work to do to build it in GitHub Actions). I think it sounds promising with stereo OPL3 VGMs:

EndlessBreak_Dual_YMF825.zip

With mono sounds however, you can hear that the two chips are not perfectly synchronised. For example, this is a mono OPL2 soundtrack, but when played on dual YMF825s, you can hear some stereo separation in the higher frequencies such as the percussion:

NewSan_Dual_YMF825.zip

It would certainly be interesting to find out if using the same clock for both chips would solve this problem!

[denjhang]

In-phase clocks don't seem to solve this problem. Because it is rumored that the initial phase of Yamaha FM is random.

[denjhang]

I personally think you can ignore the phase difference and take this as the difference and characteristic of dual YMF825 and YMF262. If the dual YMF825 and YMF262 were exactly the same, then I think it would be less interesting.

[denjhang]

If you can provide interesting OPL3 VGM files like EndlessBreak, I'd like to hear that too.

[danielrfry]

Yes, it's still an interesting experiment even if it's not possible to synchronise the two YMF825s perfectly.

I've pushed the stereo code, the builds are here: https://github.com/danielrfry/opl2sd1/actions/runs/4736826783 There are now two firmware images, one for mono and one for stereo operation.

If you'd like to try it, connect both YMF825 modules to the same SPI bus, with pin 6 → left channel YMF825 CS, pin 7 → right channel YMF825 CS.

(Please note I've changed the default pin assignments, so pin 6 is now used instead of pin 1 for CS in the mono firmware too. This is so that I can use pins 0 and 1 for debugging via UART. The documentation is not yet updated).

Endless Break by Pigu is on Battle of the Bits!

[denjhang]

I'm going to make a new version of the schematic diagram and PCB, and I plan to do advanced design. I feel that to play all OPL3 tracks perfectly, four chips are needed, because some tracks use all 18 channels at the same time, and the channels are still not enough. No matter how you schedule it . So I'm going to add 4 SD-1 module designs that don't currently exist. I hope you can make pin 8, 9 (or even more) as chip select for the third and fourth YMF825. In other words, the current chip selection situation is as follows: pin6->CS_L pin7->CS_R pin8->CS_L2 pin9->CS_R2

[danielrfry]

I think there may still be bugs in the channel allocator, so it might be possible to improve the performance further on 1 or 2 chips. I'd like to work some more on that when I have more time (I just needed a break from it for a little while!)

But if you'd like to build the 4 chip device anyway, I'd certainly like to see it and will be happy to update the code to support that. We can continue the discussion of that over on issue #7. Thanks!