Closed gmtii closed 10 years ago
why you close this issue? do you solved it?
because it seems to be related to a xrx200 eth driver issue with this board and not an u-boot problem.
On Sun, Mar 2, 2014 at 3:24 PM, dpeddi notifications@github.com wrote:
why you close this issue? do you solved it?
Reply to this email directly or view it on GitHubhttps://github.com/danielschwierzeck/u-boot-lantiq/issues/1#issuecomment-36456744 .
Esteban Benito estebanjbs@gmail.com
Gmtii I need to get in contact with you to solve same issue on different router with same soc
What can I do for you? El 08/06/2014 07:11, "dpeddi" notifications@github.com escribió:
Gmtii I need to get in contact with you to solve same issue on different router with same soc
— Reply to this email directly or view it on GitHub https://github.com/danielschwierzeck/u-boot-lantiq/issues/1#issuecomment-45429406 .
How you solved network issue with payload > 15 into openwrt?
How to get pci working?
Antonios Vamporakis found the issue: " try running tcpdump on the board while pinging it from a different machine. If tcpdump complains about packets being 4 bytes too short, you are affected by the DMA CRC issue. Try setting the DMA CRC length to 0 in the xrx200 eth driver. "
How you solved network issue with payload > 15 into openwrt?
How to get pci working?
— Reply to this email directly or view it on GitHub https://github.com/danielschwierzeck/u-boot-lantiq/issues/1#issuecomment-45434302 .
Yes, correct:
This fixed... //int len = (desc->ctl & LTQ_DMA_SIZE_MASK) - ETH_FCS_LEN; int len = (desc->ctl & LTQ_DMA_SIZE_MASK);
But the driver should be able to auto-detect this or we sould configure it using device-tree
About pci:
I get only this root@OpenWrt:/# dmesg | grep PCI [ 1.236000] PCI: CLS 0 bytes, default 32 and root@OpenWrt:/# cat /proc/bus/pci/devices root@OpenWrt:/# is empty.
about pci again:
I see your patch... http://foro.seguridadwireless.net/openwrt/(desarrollo)-openwrt-en-astoria-arv7519rw22-livebox-2-1/msg306782/#msg306782 I tried to apply it, but pci don't work for me... I get these error... root@OpenWrt:/# dmesg | grep ifxpcie [ 0.284000] ifx_pcie_wait_phy_link_up timeout [ 0.500000] ifx_pcie_wait_phy_link_up timeout [ 0.716000] ifx_pcie_wait_phy_link_up timeout [ 0.932000] ifx_pcie_wait_phy_link_up timeout [ 1.148000] ifx_pcie_wait_phy_link_up timeout
maybe I'm using wrong phy firmware?
Do you have pci and pcie sections in your dts file?
about pci again:
I see your patch...
http://foro.seguridadwireless.net/openwrt/(desarrollo)-openwrt-en-astoria-arv7519rw22-livebox-2-1/msg306782/#msg306782 I tried to apply it, but pci don't work for me... I get these error... root@OpenWrt:/# dmesg | grep ifxpcie [ 0.284000] ifx_pcie_wait_phy_link_up timeout [ 0.500000] ifx_pcie_wait_phy_link_up timeout [ 0.716000] ifx_pcie_wait_phy_link_up timeout [ 0.932000] ifx_pcie_wait_phy_link_up timeout [ 1.148000] ifx_pcie_wait_phy_link_up timeout
maybe I'm using wrong phy firmware?
— Reply to this email directly or view it on GitHub https://github.com/danielschwierzeck/u-boot-lantiq/issues/1#issuecomment-45450994 .
yes I have them, but I need both for pci? However inside vendor rom dump I haven't seen any reference to pcie
Eddi
Can you post complete bootlog and router/board model? El 14/06/2014 10:40, "dpeddi" notifications@github.com escribió:
yes I have them, but I need both for pci? However inside vendor rom dump I haven't seen any reference to pcie
Eddi
— Reply to this email directly or view it on GitHub https://github.com/danielschwierzeck/u-boot-lantiq/issues/1#issuecomment-46083365 .
gmtii,
I have the same board as dpeddi, it is the arcadyan VGV7519, this is my bootlog:
ROM VER: 1.0.5 CFG 01
U-Boot 2014.04-g1702a40-dirty (Jun 21 2014 - 16:13:24) VGV7519
Board: Arcadyan VGV7519 VRX288 Board SoC: Lantiq VRX288 v1.1 CPU: 500 MHz IO: 250 MHz BUS: 250 MHz BOOT: NOR DRAM: 64 MiB Flash: 16 MiB *\ Warning - bad CRC, using default environment
In: serial Out: serial Err: serial Net: firmware: using built-in firmware lantiq/vrx200_phy11g_a1x.fw ltq-eth Hit any key to stop autoboot: 0 Wrong Image Format for bootm command ERROR: can't get kernel image! VGV7519 # bootm 0xB0080000
Image Name: MIPS OpenWrt Linux-3.10.36 Created: 2014-06-21 11:50:30 UTC Image Type: MIPS Linux Kernel Image (lzma compressed) Data Size: 1414748 Bytes = 1.3 MiB Load Address: 80002000 Entry Point: 80002000 Verifying Checksum ... OK Uncompressing Kernel Image ... OK
Starting kernel ...
[ 0.000000] Linux version 3.10.36 (thelizard@ubuntu) (gcc version 4.8.3 (OpenWrt/Linaro GCC 4.8-2014.04 r41296) ) #1 Sat Jun 21 13:50:23 CEST 2014
[ 0.000000] SoC: VR9 rev 1.1
[ 0.000000] bootconsole [early0] enabled
[ 0.000000] CPU revision is: 00019555 (MIPS 34Kc)
[ 0.000000] Determined physical RAM map:
[ 0.000000] memory: 04000000 @ 00000000 (usable)
[ 0.000000] Initrd not found or empty - disabling initrd
[ 0.000000] Zone ranges:
[ 0.000000] Normal [mem 0x00000000-0x03ffffff]
[ 0.000000] Movable zone start for each node
[ 0.000000] Early memory node ranges
[ 0.000000] node 0: [mem 0x00000000-0x03ffffff]
[ 0.000000] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes.
[ 0.000000] Primary data cache 32kB, 4-way, VIPT, cache aliases, linesize 32 bytes
[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 16256
[ 0.000000] Kernel command line: console=ttyLTQ0,115200 init=/etc/preinit
[ 0.000000] PID hash table entries: 256 (order: -2, 1024 bytes)
[ 0.000000] Dentry cache hash table entries: 8192 (order: 3, 32768 bytes)
[ 0.000000] Inode-cache hash table entries: 4096 (order: 2, 16384 bytes)
[ 0.000000] Writing ErrCtl register=0007cf41
[ 0.000000] Readback ErrCtl register=0007cf41
[ 0.000000] Memory: 60476k/65536k available (3008k kernel code, 5060k reserved, 1018k data, 188k init, 0k highmem)
[ 0.000000] NR_IRQS:256
[ 0.000000] CPU Clock: 500MHz
[ 0.000000] Calibrating delay loop... 332.54 BogoMIPS (lpj=665088)
[ 0.032000] pid_max: default: 32768 minimum: 301
[ 0.036000] Mount-cache hash table entries: 512
[ 0.040000] pinctrl core: initialized pinctrl subsystem
[ 0.044000] NET: Registered protocol family 16
[ 0.056000] pinctrl-xway 1e100b10.pinmux: Init done
[ 0.060000] dma-xway 1e104100.dma: Init done - hw rev: 7, ports: 7, channels: 28
[ 0.068000] dcdc-xrx200 1f106a00.dcdc: Core Voltage : 1016 mV
[ 0.072000] arch/mips/pci/ifxmips_pcie_vr9.h:pcie_device_rst_assert[185]
[ 0.184000] arch/mips/pci/ifxmips_pcie_vr9.h:pcie_device_rst_deassert[193]
[ 0.284000] ifx_pcie_wait_phy_link_up timeout
[ 0.288000] arch/mips/pci/ifxmips_pcie_vr9.h:pcie_device_rst_assert[185]
[ 0.400000] arch/mips/pci/ifxmips_pcie_vr9.h:pcie_device_rst_deassert[193]
[ 0.500000] ifx_pcie_wait_phy_link_up timeout
[ 0.504000] arch/mips/pci/ifxmips_pcie_vr9.h:pcie_device_rst_assert[185]
[ 0.616000] arch/mips/pci/ifxmips_pcie_vr9.h:pcie_device_rst_deassert[193]
[ 0.716000] ifx_pcie_wait_phy_link_up timeout
[ 0.720000] arch/mips/pci/ifxmips_pcie_vr9.h:pcie_device_rst_assert[185]
[ 0.832000] arch/mips/pci/ifxmips_pcie_vr9.h:pcie_device_rst_deassert[193]
[ 0.932000] ifx_pcie_wait_phy_link_up timeout
[ 0.936000] arch/mips/pci/ifxmips_pcie_vr9.h:pcie_device_rst_assert[185]
[ 1.048000] arch/mips/pci/ifxmips_pcie_vr9.h:pcie_device_rst_deassert[193]
[ 1.148000] ifx_pcie_wait_phy_link_up timeout
[ 1.152000] pcie_rc_initialize link up failed!!!!!
[ 1.164000] bio: create slab
[ 11.276000] NET: Registered protocol family 10 [ 11.284000] NET: Registered protocol family 8 [ 11.288000] NET: Registered protocol family 20 [ 11.300000] sit: IPv6 over IPv4 tunneling driver [ 11.316000] PPP generic driver version 2.4.2 [ 11.336000] nf_conntrack version 0.5.0 (947 buckets, 3788 max) [ 11.352000] ip6_tables: (C) 2000-2006 Netfilter Core Team [ 11.388000] MEI CPE Driver, Version 1.2.0
11.392000 Copyright 2009, Infineon Technologies AG
Lantiq CPE API Driver version: DSL CPE API V4.11.4 [ 11.420000] [ 11.420000] Predefined debug level: 2 [ 11.428000] Loading modules backported from Linux version master-2014-05-22-0-gf2032ea [ 11.436000] Backport generated by backports.git backports-20140320-37-g5c33da0 [ 11.444000] ip_tables: (C) 2000-2006 Netfilter Core Team [ 11.456000] Infineon Technologies DEU driver version 2.0.0 [ 11.460000] IFX DEU DES initialized (multiblock). [ 11.468000] IFX DEU AES initialized (multiblock). [ 11.472000] IFX DEU ARC4 initialized (multiblock). [ 11.476000] IFX DEU SHA1 initialized. [ 11.480000] IFX DEU MD5 initialized. [ 11.484000] IFX DEU SHA1_HMAC initialized. [ 11.488000] IFX DEU MD5_HMAC initialized. [ 11.508000] NET: Registered protocol family 24 [ 11.528000] xt_time: kernel timezone is -0000 [ 11.552000] cfg80211: Calling CRDA to update world regulatory domain [ 11.556000] cfg80211: World regulatory domain updated: [ 11.560000] cfg80211: DFS Master region: unset [ 11.564000] cfg80211: (start_freq - end_freq @ bandwidth), (max_antenna_gain, max_eirp), (dfs_cac_time) [ 11.576000] cfg80211: (2402000 KHz - 2472000 KHz @ 40000 KHz), (N/A, 2000 mBm), (N/A) [ 11.584000] cfg80211: (2457000 KHz - 2482000 KHz @ 40000 KHz), (N/A, 2000 mBm), (N/A) [ 11.592000] cfg80211: (2474000 KHz - 2494000 KHz @ 20000 KHz), (N/A, 2000 mBm), (N/A) [ 11.600000] cfg80211: (5170000 KHz - 5250000 KHz @ 80000 KHz), (N/A, 2000 mBm), (N/A) [ 11.608000] cfg80211: (5735000 KHz - 5835000 KHz @ 80000 KHz), (N/A, 2000 mBm), (N/A) [ 11.616000] cfg80211: (57240000 KHz - 63720000 KHz @ 2160000 KHz), (N/A, 0 mBm), (N/A) [ 18.052000] device eth0 entered promiscuous mode [ 18.060000] br-lan: port 1(eth0) entered forwarding state [ 18.064000] br-lan: port 1(eth0) entered forwarding state [ 20.068000] br-lan: port 1(eth0) entered forwarding state procd: - init complete -
Ok, did you find the pcie reset gpio for your board? as default, openwrt has gpio 238 (38) defined:
You need to update both #define for your particular gpio:
On ARV7519RW, pcie reset gpio is 21 ( http://wiki.openwrt.org/toh/arcadyan/arv7519 )
Esteban.
On Sun, Jun 22, 2014 at 4:21 PM, The-Lizard notifications@github.com wrote:
gmtii,
I have the same board as dpeddi, it is the arcadyan VGV7519, this is my bootlog:
ROM VER: 1.0.5 CFG 01
U-Boot 2014.04-g1702a40-dirty (Jun 21 2014 - 16:13:24) VGV7519
Board: Arcadyan VGV7519 VRX288 Board SoC: Lantiq VRX288 v1.1 CPU: 500 MHz IO: 250 MHz BUS: 250 MHz BOOT: NOR DRAM: 64 MiB Flash: 16 MiB *\ Warning - bad CRC, using default environment
In: serial Out: serial Err: serial Net: firmware: using built-in firmware lantiq/vrx200_phy11g_a1x.fw ltq-eth Hit any key to stop autoboot: 0 Wrong Image Format for bootm command ERROR: can't get kernel image! VGV7519 # bootm 0xB0080000 Booting kernel from Legacy Image at b0080000 ...
Image Name: MIPS OpenWrt Linux-3.10.36 Created: 2014-06-21 11:50:30 UTC Image Type: MIPS Linux Kernel Image (lzma compressed) Data Size: 1414748 Bytes = 1.3 MiB Load Address: 80002000 Entry Point: 80002000 Verifying Checksum ... OK Uncompressing Kernel Image ... OK
Starting kernel ...
[ 0.000000] Linux version 3.10.36 (thelizard@ubuntu) (gcc version 4.8.3 (OpenWrt/Linaro GCC 4.8-2014.04 r41296) ) #1 https://github.com/danielschwierzeck/u-boot-lantiq/issues/1 Sat Jun 21 13:50:23 CEST 2014 [ 0.000000] SoC: VR9 rev 1.1 [ 0.000000] bootconsole [early0] enabled [ 0.000000] CPU revision is: 00019555 (MIPS 34Kc) [ 0.000000] Determined physical RAM map: [ 0.000000] memory: 04000000 @ 00000000 (usable) [ 0.000000] Initrd not found or empty - disabling initrd [ 0.000000] Zone ranges: [ 0.000000] Normal [mem 0x00000000-0x03ffffff] [ 0.000000] Movable zone start for each node [ 0.000000] Early memory node ranges [ 0.000000] node 0: [mem 0x00000000-0x03ffffff] [ 0.000000] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes. [ 0.000000] Primary data cache 32kB, 4-way, VIPT, cache aliases, linesize 32 bytes [ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 16256 [ 0.000000] Kernel command line: console=ttyLTQ0,115200 init=/etc/preinit [ 0.000000] PID hash table entries: 256 (order: -2, 1024 bytes) [ 0.000000] Dentry cache hash table entries: 8192 (order: 3, 32768 bytes) [ 0.000000] Inode-cache hash table entries: 4096 (order: 2, 16384 bytes) [ 0.000000] Writing ErrCtl register=0007cf41 [ 0.000000] Readback ErrCtl register=0007cf41 [ 0.000000] Memory: 60476k/65536k available (3008k kernel code, 5060k reserved, 1018k data, 188k init, 0k highmem) [ 0.000000] NR_IRQS:256 [ 0.000000] CPU Clock: 500MHz [ 0.000000] Calibrating delay loop... 332.54 BogoMIPS (lpj=665088) [ 0.032000] pid_max: default: 32768 minimum: 301 [ 0.036000] Mount-cache hash table entries: 512 [ 0.040000] pinctrl core: initialized pinctrl subsystem [ 0.044000] NET: Registered protocol family 16 [ 0.056000] pinctrl-xway 1e100b10.pinmux: Init done [ 0.060000] dma-xway 1e104100.dma: Init done - hw rev: 7, ports: 7, channels: 28 [ 0.068000] dcdc-xrx200 1f106a00.dcdc: Core Voltage : 1016 mV [ 0.072000] arch/mips/pci/ifxmips_pcie_vr9.h:pcie_device_rst_assert[185] [ 0.184000] arch/mips/pci/ifxmips_pcie_vr9.h:pcie_device_rst_deassert[193] [ 0.284000] ifx_pcie_wait_phy_link_up timeout [ 0.288000] arch/mips/pci/ifxmips_pcie_vr9.h:pcie_device_rst_assert[185] [ 0.400000] arch/mips/pci/ifxmips_pcie_vr9.h:pcie_device_rst_deassert[193] [ 0.500000] ifx_pcie_wait_phy_link_up timeout [ 0.504000] arch/mips/pci/ifxmips_pcie_vr9.h:pcie_device_rst_assert[185] [ 0.616000] arch/mips/pci/ifxmips_pcie_vr9.h:pcie_device_rst_deassert[193] [ 0.716000] ifx_pcie_wait_phy_link_up timeout [ 0.720000] arch/mips/pci/ifxmips_pcie_vr9.h:pcie_device_rst_assert[185] [ 0.832000] arch/mips/pci/ifxmips_pcie_vr9.h:pcie_device_rst_deassert[193] [ 0.932000] ifx_pcie_wait_phy_link_up timeout [ 0.936000] arch/mips/pci/ifxmips_pcie_vr9.h:pcie_device_rst_assert[185] [ 1.048000] arch/mips/pci/ifxmips_pcie_vr9.h:pcie_device_rst_deassert[193] [ 1.148000] ifx_pcie_wait_phy_link_up timeout [ 1.152000] pcie_rc_initialize link up failed!!!!! [ 1.164000] bio: create slab at 0 [ 1.168000] gpio-stp-xway 1e100bb0.stp: Init done [ 1.172000] usbcore: registered new interface driver usbfs [ 1.176000] usbcore: registered new interface driver hub [ 1.180000] usbcore: registered new device driver usb [ 1.184000] Switching to clocksource MIPS [ 1.192000] NET: Registered protocol family 2 [ 1.196000] TCP established hash table entries: 512 (order: 0, 4096 bytes) [ 1.200000] TCP bind hash table entries: 512 (order: -1, 2048 bytes) [ 1.208000] TCP: Hash tables configured (established 512 bind 512) [ 1.216000] TCP: reno registered [ 1.216000] UDP hash table entries: 256 (order: 0, 4096 bytes) [ 1.224000] UDP-Lite hash table entries: 256 (order: 0, 4096 bytes) [ 1.232000] NET: Registered protocol family 1 [ 1.236000] gptu: totally 6 16-bit timers/counters [ 1.240000] gptu: misc_register on minor 63 [ 1.244000] gptu: succeeded to request irq 126 [ 1.248000] gptu: succeeded to request irq 127 [ 1.252000] gptu: succeeded to request irq 128 [ 1.256000] gptu: succeeded to request irq 129 [ 1.264000] gptu: succeeded to request irq 130 [ 1.268000] gptu: succeeded to request irq 131 [ 1.272000] phy-xrx200 gphy-xrx200.5: requesting lantiq/vr9_phy11g_a1x.bin [ 1.280000] phy-xrx200 gphy-xrx200.5: booting GPHY0 firmware at 38C0000 [ 1.288000] phy-xrx200 gphy-xrx200.5: booting GPHY1 firmware at 38C0000 [ 1.396000] squashfs: version 4.0 (2009/01/31) Phillip Lougher [ 1.404000] jffs2: version 2.2 (NAND) (SUMMARY) (LZMA) (RTIME) (CMODE_PRIORITY) (c) 2001-2006 Red Hat, Inc. [ 1.412000] msgmni has been set to 118 [ 1.416000] io scheduler noop registered [ 1.420000] io scheduler deadline registered (default) [ 1.428000] 1e100c00.serial: ttyLTQ0 at MMIO 0x1e100c00 (irq = 112) is a lantiq,asc [ 1.436000] console [ttyLTQ0] enabled, bootconsole disabled [ 1.436000] console [ttyLTQ0] enabled, bootconsole disabled [ 1.448000] ltq_nor: Found 1 x16 devices at 0x0 in 16-bit bank. Manufacturer ID 0x00007f Chip ID 0x0022cb [ 1.456000] Amd/Fujitsu Extended Query Table at 0x0040 [ 1.464000] Amd/Fujitsu Extended Query version 1.1. [ 1.468000] number of CFI chips: 1 [ 1.472000] 3 ofpart partitions found on MTD device ltq_nor [ 1.476000] Creating 3 MTD partitions on "ltq_nor": [ 1.480000] 0x000000000000-0x000000040000 : "uboot" [ 1.488000] 0x000000060000-0x000000070000 : "uboot_env" [ 1.492000] 0x000000080000-0x000001000000 : "firmware" [ 1.496000] mtd: partition "firmware" extends beyond the end of device "ltq_nor" -- size truncated to 0x780000 [ 1.508000] 0x0000001d969c-0x000000800000 : "rootfs" [ 1.512000] mtd: partition "rootfs" must either start or end on erase block boundary or be smaller than an erase block -- forcing read-only [ 1.528000] mtd: device 3 (rootfs) set to be root filesystem [ 1.532000] mtd: partition "rootfs_data" created automatically, ofs=0x3f0000, len=0x410000 [ 1.540000] 0x0000003f0000-0x000000800000 : "rootfs_data" [ 1.672000] libphy: lantiq,xrx200-mdio: probed [ 1.680000] net-xrx200: invalid MAC, using random [ 1.684000] eth0: attached PHY Lantiq XWAY VR9 GPHY 11G v1.3 [ 1.692000] eth0: attached PHY Lantiq XWAY VR9 GPHY 11G v1.3 [ 1.700000] eth0: attached PHY Lantiq XWAY VR9 GPHY 11G v1.4 [ 1.708000] eth0: attached PHY Lantiq XWAY VR9 GPHY 11G v1.4 [ 1.716000] net-xrx200: invalid MAC, using random [ 1.720000] eth1: attached PHY Lantiq XWAY VR9 GPHY 11G v1.3 [ 1.728000] wdt 1f8803f0.watchdog: Init done [ 1.732000] leds-gpio gpio-leds.7: pins are not configured from the driver [ 1.744000] TCP: cubic registered [ 1.744000] NET: Registered protocol family 17 [ 1.752000] 8021q: 802.1Q VLAN Support v1.8 [ 1.760000] UBIFS error (pid 1): ubifs_mount: cannot open "ubi0:rootfs", error -19 [ 1.772000] VFS: Mounted root (squashfs filesystem) readonly on device 31:3. [ 1.776000] Freeing unused kernel memory: 188K (803f1000 - 80420000) [ 2.700000] eth0: port 0 got link procd: Console is alive procd: - watchdog - [ 4.572000] IFXUSB: ifxusb_hcd: version 3.2 B110801 [ 4.576000] Chip Version :01c0 BurstSize=0 [ 5.180000] IFXUSB: USB core #0 soft-reset [ 5.484000] IFXUSB: USB core #0 soft-reset [ 5.488000] ifxusb_hcd ifxusb_hcd: IFX USB Controller [ 5.492000] ifxusb_hcd ifxusb_hcd: new USB bus registered, assigned bus number 1 [ 5.500000] ifxusb_hcd ifxusb_hcd: irq 62, io mem 0xbe101000 [ 5.504000] IFXUSB: Init: Power Port (0) [ 5.512000] hub 1-0:1.0: USB hub found [ 5.512000] hub 1-0:1.0: 1 port detected [ 6.016000] IFXUSB: USB core #1 https://github.com/danielschwierzeck/u-boot-lantiq/issues/1 soft-reset [ 6.320000] IFXUSB: USB core #1 https://github.com/danielschwierzeck/u-boot-lantiq/issues/1 soft-reset [ 6.324000] ifxusb_hcd ifxusb_hcd: IFX USB Controller [ 6.328000] ifxusb_hcd ifxusb_hcd: new USB bus registered, assigned bus number 2 [ 6.336000] ifxusb_hcd ifxusb_hcd: irq 91, io mem 0xbe106000 [ 6.340000] IFXUSB: Init: Power Port (0) [ 6.344000] hub 2-0:1.0: USB hub found [ 6.348000] hub 2-0:1.0: 1 port detected [ 6.352000] ifxusb_hcd ifxusb_hcd: requested GPIO 232 procd: - preinit - Press the [f] key and hit [enter] to enter failsafe mode Press the [1], [2], [3] or [4] key and hit [enter] to select the debug level jffs2 is ready jffs2 is ready [ 9.832000] jffs2: notice: (267) jffs2_build_xattr_subsystem: complete building xattr subsystem, 1 of xdatum (0 unchecked, 0 orphan) and 9 of xref (0 dead, 2 orphan) found. switching to overlay procd: - early - procd: - watchdog - procd: - ubus - procd: - init - Please press Enter to activate this console. [ 11.252000] IFXOS, Version 1.5.14 (c) Copyright 2009, Lantiq Deutschland GmbH
[ 11.276000] NET: Registered protocol family 10 [ 11.284000] NET: Registered protocol family 8 [ 11.288000] NET: Registered protocol family 20 [ 11.300000] sit: IPv6 over IPv4 tunneling driver [ 11.316000] PPP generic driver version 2.4.2 [ 11.336000] nf_conntrack version 0.5.0 (947 buckets, 3788 max) [ 11.352000] ip6_tables: (C) 2000-2006 Netfilter Core Team [ 11.388000] MEI CPE Driver, Version 1.2.0
11.392000 http://c Copyright 2009, Infineon Technologies AG MEI CPE - MEI CPE - MEI CPE - MEI CPE
Lantiq CPE API Driver version: DSL CPE API V4.11.4 [ 11.420000] [ 11.420000] Predefined debug level: 2 [ 11.428000] Loading modules backported from Linux version master-2014-05-22-0-gf2032ea [ 11.436000] Backport generated by backports.git backports-20140320-37-g5c33da0 [ 11.444000] ip_tables: (C) 2000-2006 Netfilter Core Team [ 11.456000] Infineon Technologies DEU driver version 2.0.0 [ 11.460000] IFX DEU DES initialized (multiblock). [ 11.468000] IFX DEU AES initialized (multiblock). [ 11.472000] IFX DEU ARC4 initialized (multiblock). [ 11.476000] IFX DEU SHA1 initialized. [ 11.480000] IFX DEU MD5 initialized. [ 11.484000] IFX DEU SHA1_HMAC initialized. [ 11.488000] IFX DEU MD5_HMAC initialized. [ 11.508000] NET: Registered protocol family 24 [ 11.528000] xt_time: kernel timezone is -0000 [ 11.552000] cfg80211: Calling CRDA to update world regulatory domain [ 11.556000] cfg80211: World regulatory domain updated: [ 11.560000] cfg80211: DFS Master region: unset [ 11.564000] cfg80211: (start_freq - end_freq @ bandwidth), (max_antenna_gain, max_eirp), (dfs_cac_time) [ 11.576000] cfg80211: (2402000 KHz - 2472000 KHz @ 40000 KHz), (N/A, 2000 mBm), (N/A) [ 11.584000] cfg80211: (2457000 KHz - 2482000 KHz @ 40000 KHz), (N/A, 2000 mBm), (N/A) [ 11.592000] cfg80211: (2474000 KHz - 2494000 KHz @ 20000 KHz), (N/A, 2000 mBm), (N/A) [ 11.600000] cfg80211: (5170000 KHz - 5250000 KHz @ 80000 KHz), (N/A, 2000 mBm), (N/A) [ 11.608000] cfg80211: (5735000 KHz - 5835000 KHz @ 80000 KHz), (N/A, 2000 mBm), (N/A) [ 11.616000] cfg80211: (57240000 KHz - 63720000 KHz @ 2160000 KHz), (N/A, 0 mBm), (N/A) [ 18.052000] device eth0 entered promiscuous mode [ 18.060000] br-lan: port 1(eth0) entered forwarding state [ 18.064000] br-lan: port 1(eth0) entered forwarding state [ 20.068000] br-lan: port 1(eth0) entered forwarding state procd: - init complete -
— Reply to this email directly or view it on GitHub https://github.com/danielschwierzeck/u-boot-lantiq/issues/1#issuecomment-46783762 .
Esteban Benito estebanjbs@gmail.com
Does PCIe offer backwards compatibility for PCI? We have seen that for lantiq xrx200 PCI is disabled, while PCIe is enabled. The WIFI chip on the board (RALink RT5362F) only seems to have a PCI bus.
What is the best way to find the reset pin (as all the packages are BGA)?
Astoria ARV7519RW has wifi card on pcie bus ... lspci outputs anything?
Post original oem firmware bootlog... maybe pcie reset gpio is there...
On Mon, Jun 23, 2014 at 8:43 AM, The-Lizard notifications@github.com wrote:
Does PCIe offer backwards compatibility for PCI? We have seen that for lantiq xrx200 PCI is disabled, while PCIe is enabled. The WIFI chip on the board (RALink RT5362F) only seems to have a PCI bus.
What is the best way to find the reset pin (as all the packages are BGA)?
— Reply to this email directly or view it on GitHub https://github.com/danielschwierzeck/u-boot-lantiq/issues/1#issuecomment-46814392 .
Esteban Benito estebanjbs@gmail.com
original bootlog is posted on the openwrt device page: http://wiki.openwrt.org/toh/arcadyan/vgv7519
but there is nothing useful (as nothing interesting really comes out): ROM VER: 1.0.5 CFG 01
Wireless ADSL Gateway VR9 Loader v3.00.06 build Oct 20 2011 15:15:46
[1] .[1(9)][3] [1] done In c_entry() function ... install_exception ---- end of bootlog
Did the ARV7519 output it by default? How did you discover the bootloader password? I have only found some SHA-1 hashes...
ROM:805BE4D4 li $a0, 0x15 ROM:805BE4D8 jal ifx_gpio_pin_reserve ROM:805BE4DC li $a1, 9 ROM:805BE4E0 li $a0, 0x15 ROM:805BE4E4 jal ifx_gpio_output_set ROM:805BE4E8 li $a1, 9 ROM:805BE4EC li $a0, 0x15 ROM:805BE4F0 jal ifx_gpio_dir_out_set ROM:805BE4F4 li $a1, 9 ROM:805BE4F8 li $a0, 0x15 ROM:805BE4FC jal ifx_gpio_altsel0_clear ROM:805BE500 li $a1, 9 ROM:805BE504 li $a0, 0x15 ROM:805BE508 jal ifx_gpio_altsel1_clear ROM:805BE50C li $a1, 9 ROM:805BE510 li $a0, 0x15 ROM:805BE514 jal ifx_gpio_open_drain_set ROM:805BE518 li $a1, 9 ROM:805BE51C li $a0, 0x15 ROM:805BE520 jal ifx_gpio_output_clear ROM:805BE524 li $a1, 9
hmmm, change 238 (38) gpio to 221 (21) in
./trunk/target/linux/lantiq/patches-3.10/0001-MIPS-lantiq-add-pcie-driver.patch
make clean, recompile and flash ...
ARV7519 output complete log as default, and boot password was stored in clear text in boot dump :-)
Esteban.
On Mon, Jun 23, 2014 at 10:01 AM, dpeddi notifications@github.com wrote:
ROM:805BE4D4 li $a0, 0x15 ROM:805BE4D8 jal ifx_gpio_pin_reserve ROM:805BE4DC li $a1, 9 ROM:805BE4E0 li $a0, 0x15 ROM:805BE4E4 jal ifx_gpio_output_set ROM:805BE4E8 li $a1, 9 ROM:805BE4EC li $a0, 0x15 ROM:805BE4F0 jal ifx_gpio_dir_out_set ROM:805BE4F4 li $a1, 9 ROM:805BE4F8 li $a0, 0x15 ROM:805BE4FC jal ifx_gpio_altsel0_clear ROM:805BE500 li $a1, 9 ROM:805BE504 li $a0, 0x15 ROM:805BE508 jal ifx_gpio_altsel1_clear ROM:805BE50C li $a1, 9 ROM:805BE510 li $a0, 0x15 ROM:805BE514 jal ifx_gpio_open_drain_set ROM:805BE518 li $a1, 9 ROM:805BE51C li $a0, 0x15 ROM:805BE520 jal ifx_gpio_output_clear ROM:805BE524 li $a1, 9
— Reply to this email directly or view it on GitHub https://github.com/danielschwierzeck/u-boot-lantiq/issues/1#issuecomment-46820587 .
Esteban Benito estebanjbs@gmail.com
Hi Esteban,
Already tried 14 days ago root@OpenWrt:/# dmesg | grep ifxpcie [ 0.284000] ifx_pcie_wait_phy_link_up timeout [ 0.500000] ifx_pcie_wait_phy_link_up timeout [ 0.716000] ifx_pcie_wait_phy_link_up timeout [ 0.932000] ifx_pcie_wait_phy_link_up timeout [ 1.148000] ifx_pcie_wait_phy_link_up timeout
I think we have a pci bus and nota a pci-e..
ARV7519 output complete log as default, and boot password was stored in clear text in boot dump :-)
Hi @gmtii ! Could you share a boot password with me?
hi,
Ping fails when booting Openwrt from this u-boot on arv7519rw22 board (http://wiki.openwrt.org/toh/arcadyan/arv7519) (support added on this fork: https://github.com/gmtii/u-boot-lantiq/tree/openwrt/v2013.10
in u-boot:
U-Boot 2013.10-openwrt5-dirty (Jan 07 2014 - 10:29:58) arv7519rw
Board: Lantiq ARV7519RW VRX200 Family Board SoC: Lantiq VRX288 v1.2 CPU: 500 MHz IO: 250 MHz BUS: 250 MHz BOOT: NOR DRAM: 128 MiB Flash: 32 MiB In: serial Out: serial Err: serial Net: ltq-eth Hit any key to stop autoboot: 0 arv7519rw # ping 192.168.1.100 ltq_phy: addr 0, link 0, speed 10, duplex 0 ltq_phy: addr 17, link 0, speed 10, duplex 0 ltq_phy: addr 19, link 1, speed 100, duplex 1 Using ltq-eth device host 192.168.1.100 is alive arv7519rw #
from Openwrt I can only ping host if payload is <15:
root@OpenWrt:/# ping -s 14 192.168.1.100 PING 192.168.1.100 (192.168.1.100): 14 data bytes 22 bytes from 192.168.1.100: seq=0 ttl=64 time=0.483 ms
Ping is ok in oem u-boot booting same Openwrt image, so it seems related to net hw initialization done by this u-boot .
Thank you very much.