Closed gmtii closed 10 years ago
I have not seen this problem on my Lantiq EASY80920 which has a VR9 v1.1. Which branch did you test?
On Danube SoC there was a bug in BootROM code which incorrectly setup the pinmux for a address line needed for 32 MB flash devices. I don't know if VR9 (esp. v1.1) still has that bug. Could you send me a dump of the original bootloader and a full boot log?
Bootlogs: http://wiki.openwrt.org/toh/arcadyan/arv7519
And original boot dump: https://www.dropbox.com/s/6z6r11j5vh2d30t/boot_original_livebox21.bin.gz
it is really strange... just now I flashed 512kb (board configuration partition) at 0xB1F80000 and seems correct after reset so seems ok for high flash addresses ? ... and problems begin after entering command 'erase all' ; now, I enter UART mode and upload RAM uboot but now I can't rewrite u-boot...
Esteban.
On Wed, Mar 5, 2014 at 9:54 PM, Daniel Schwierzeck <notifications@github.com
wrote:
I have not seen this problem on my Lantiq EASY80920 which has a VR9 v1.1. Which branch did you test?
On Danube SoC there was a bug in BootROM code which incorrectly setup the pinmux for a address line needed for 32 MB flash devices. I don't know if VR9 (esp. v1.1) still has that bug. Could you send me a dump of the original bootloader and a full boot log?
Reply to this email directly or view it on GitHubhttps://github.com/danielschwierzeck/u-boot-lantiq/issues/2#issuecomment-36798890 .
Esteban Benito estebanjbs@gmail.com
You need 25 address lines to access 32 MB flash devices. But only A0-A22 are directly connected to the external EBU interface. A23, A24 and A25 are available on the GPIO interface via pinmux. Thus adding following code to your board gpio_init() should help:
/* EBU.FLA23 as output for NOR flash / gpio_set_altfunc(24, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIROUT); / EBU.FL_A24 as output for NOR flash */ gpio_set_altfunc(13, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
optionally: /* EBU.FL_A25 as output for NOR flash */ gpio_set_altfunc(31, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
ok, it's working now... so it was my mistake not adding gpio init for that lines in this board.
thank you very much for your help! :-)
Esteban.
Hi,
I'm having some issues vr9 soc ver 1.1 booing from u-boot RAM image:
This is the log for successfully u-boot update on a 1.2 version (same flash IC):
http://pastebin.com/vBNKuY0b
And this is for a 1.1 version:
http://pastebin.com/YJcHYZ5p
It protects off sector 0 and then goes into a endless loop from 1-256 sector twice protecting all sectors... so later erase and write operations fail and u-boot is not written.
Same loop when entereing "protect off all":
http://pastebin.com/dtJJQZPP
So, maybe is there any bug with this soc ver ?
arv7519rw # bdinfo boot_params = 0x87E91F68 memstart = 0x80000000 memsize = 0x08000000 flashstart = 0xB0000000 flashsize = 0x02000000 flashoffset = 0x00000000 ethaddr = 00:01:02:03:04:05 ip_addr = 192.168.1.1 baudrate = 115200 bps
arv7519rw # flinfo
Bank # 1: CFI conformant flash (16 x 16) Size: 32 MB in 256 Sectors AMD Standard command set, Manufacturer ID: 0xC2, Device ID: 0x227E2201 Advanced Sector Protection (PPB) enabled Erase timeout: 4096 ms, write timeout: 1 ms Buffer write timeout: 3 ms, buffer size: 64 bytes
Esteban.