Closed ScApi closed 10 years ago
With cfi_flash debug enabled:
CPU: 125 MHz IO: 125 MHz BUS: 125 MHz BOOT: UART w/o EEPROM DRAM: 256 MiB flash detect cfi fwc addr b0000002 cmd f0 f0f0 16bit x 8 bit fwc addr b0000002 cmd ff ffff 16bit x 8 bit fwc addr b00000a8 cmd 98 9898 16bit x 8 bit is= cmd 51(Q) addr b0000022 is= 9898 5151 fwc addr b0000aa8 cmd 98 9898 16bit x 8 bit is= cmd 51(Q) addr b0000022 is= 9898 5151 fwc addr b0000002 cmd f0 00f0 16bit x 16 bit fwc addr b0000002 cmd ff 00ff 16bit x 16 bit fwc addr b00000a8 cmd 98 0098 16bit x 16 bit is= cmd 51(Q) addr b0000022 is= 0098 0051 fwc addr b0000aa8 cmd 98 0098 16bit x 16 bit is= cmd 51(Q) addr b0000022 is= 0098 0051 fwc addr b0000002 cmd f0 f0f0f0f0 32bit x`8 bit
ROM VER: 1.0.5 CFG 02 UART
Looks like an unaligned MMIO access. Could you re-check with openwrt/v2014.01, 2014.04 is not fully tested? Could you also check if flash_swap_addr() in arch/mips/cpu/mips32/vrx200/ebu.c is called?
Everything is working ok, made stupid mistake CFG 02 UART instead of CFG 04 UART
I'm trying to build U-boot for this board, it's similar to P-2812HNU-F1/Fx, images created with v2014.04 branch works, asc/nand, but after adding NOR Boot support or only NOR with NAND stripped out, boot goes till DRAM: 128/256 prompt (error in ddr config in Your branch) and goes back to UART mode, from what I see in similar boards there should be Flash prompt so I assume there is something wrong about My config, but even adding #CONFIG_LTQ_SUPPORT_NOR_FLASH is making this issue. Am I missing something ?