I am not able to get this component to work at all.

This is the display I am using.

https://www.buydisplay.com/spi-1280x400-7-84-inch-ips-tft-lcd-module-optl-capacitive-touch

Any assistance or advise would be greatly appreciated

Hi Kevin,

Ok boring questions first... can you confirm you ordered it in 8080-mode configuration? my driver only supports 8080 mode at the moment.

On 28/12/2023 19:36, Kevin Schlosser wrote:

This is the display I am using.

https://www.buydisplay.com/spi-1280x400-7-84-inch-ips-tft-lcd-module-optl-capacitive-touch https://www.buydisplay.com/spi-1280x400-7-84-inch-ips-tft-lcd-module-optl-capacitive-touch

Any assistance or advise would be greatly apprediated

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It is made that way. The manufacturer pre sets the display to be in I8080 mode. I did confirm this by checking the solder points that have to be soldered for it to be in I8080 mode. I checked them a few times now along with the connections as well. everything is connected correctly.

I am going to be trying to power it using an external power supply instead of the USB port. Between the ESP32 and the display I might be low on power. The ESP is not having any issues and that will typically act up if there is a low voltage issue. The display might be more sensitive to voltage drop.. Not sure.

One other thing is from looking at the C code that was written in the demo (only for stm32) it appears that there are some registers that get set based on the type of memory that is used. specifically the brand and model of the memory. I have not quite figured out what that needs to be set to because there is nothing that tell me what the memory is that is in use.

I haven't tried that particular screen from buydisplay, but I do use others from there without a problem. Some of the screens can be pretty power hungry.

Can you share the output of your serial log when your project boots? (preferrably with logging set to info or better)

On 29/12/2023 04:35, Kevin Schlosser wrote:

It is made that way. The manufacturer pre sets the display to be in I8080 mode. I did confirm this by checking the solder points that have to be soldered for it to be in I8080 mode. I checked them a few times now along with the connections as well. everything is connected correctly.

I am going to be trying to power it using an external power supply instead of the USB port. Between the ESP32 and the display I might be low on power. The ESP is not having any issues and that will typically act up if there is a low voltage issue. The display might be more sensitive to voltage drop.. Not sure.

One other thing is from looking at the C code that was written in the demo (only for stm32) it appears that there are some registers that get set based on the type of memory that is used. specifically the brand and model of the memory. I have not quite figured out what that needs to be set to because there is nothing that tell me what the memory is that is in use.

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I believe I found the issue. This is a very badly documented display but it appears to be that the display has an internal MIPI IC and buydisplay has added an MIPI to SPI/RGB bridge and that bridge defaults to SPI when powered on. So it needs to be instructed to use RGB which is what is connected to the LT683 IC. In order to make this work there is an additional 5 connections that have to be made and initialization commands need to be sent to that MIPI bridge. The documentation is very vague on this but when looking at the code examples that are provided that is what I am seeing.

Maybe you can have a look at their examples and tell me if you are seeing the same thing??...

It does, indeed, seem to have quite a lengthy setup procedure for the SSD2828 chip on there. So yes, you would need to use extra pins to talk to the SSD2828 chip and reset+initialise it before setting up the RA8876 chip.

Good spot.

On 29/12/2023 21:58, Kevin Schlosser wrote:

I believe I found the issue. This is a very badly documented display but it appears to be that the display has an internal MIPI IC and buydisplay has added an MIPI to SPI/RGB bridge and that bridge defaults to SPI when powered on. So it needs to be instructed to use RGB which is what is connected to the LT683 IC. In order to make this work there is an additional 5 connections that have to be made and initialization commands need to be sent to that MIPI bridge. The documentation is very vague on this but when looking at the code examples that are provided that is what I am seeing.

Maybe you can have a look at their examples and tell me if you are seeing the same thing??...

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Their descriptions for those pins says "For SPI bus" not "these pins are required in order to set up the display to work with the display IC" If they had stated that I would have probably gone with a different display. That's a lot of additional pins that have to be connected for the only purpose of being used a single time when the display gets initially turned on.

The other thing is if you look at the code on how it send the data it's not SPI. it's some other form of communication. so I can't even use the built in SPI in the ESPIDF to send the data.

I don't know why they are calling the connection SPI because it's not.

It may still be SPI, i didn't look at it... but their 80xx microcontroller example code doesnt have any hardware support for SPI etc so everything is bit-banged instead. They do the same for I2C too.

I would usually read the datasheet for the IC to find out what it expects, and then use their example code for the initialisation routine data for the setup.

But yes, having to use those extra pins is definitely an annoyance. We do get quite a few pins on the ESP32 but when you're driving a 16-bit parallel display you're still going to be quite limited.

Plus avoiding using the strapping pins can hinder things further.

On 29/12/2023 22:44, Kevin Schlosser wrote:

Their descriptions for those pins says "For SPI bus" not "these pins are required in order to set up the display to work with the display IC" If they had stated that I would have probably gone with a different display. That's a lot of additional pins that have to be connected for the only purpose of being used a single time when the display gets initially turned on.

The other thing is if you look at the code on how it send the data it's not SPI. it's some other form of communication. so I can't even use the built in SPI in the ESPIDF to send the data.

I don't know why they are calling the connection SPI because it's not.

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in this use case I am going to be able to use the strapping pins for some of the I8080 data pins because they don't have any pullups being used in the first 8 data pins for the display IC. so they will be in a float condition and the display isn't going to be connected to the display IC because the MIPI Bridge hasn't been set up yet. So I am pretty sure I am able to make that work without an issue.

I am going to use the same bit banging they re doing to send the init commands to the MIPI bridge. Because it appears that the MIPI bridge does have a CS line once the init commands are sent it is not going to be listening of the line is pulled low. My project was going to be using 2 ESP32-S3's because I need more pins and having to add an ADC IC and a PWM IC and also a GPIO IC to add additional pins it is cheaper and easier to just use a second ESP32-S3 and have the 2 connected together. I was originally going to use I2C but now it appears like I will be using SPI instead. That's if the MIPI bridge doesn't get all out of sorts because of it seeing those lines being used. That's if the MIPI bridge is actually using SPI.

I have done some reading elsewhere about this display being used with an ESP32 and it was said that the MIPI Bridge is not using a standard form of SPI and that SPI built into the ESPIDF is not able to be used. Whether or not that is true or not I will know soon enough.

The data sheet for the display wasn't very clear. The description also states that the display doesn't support hardware rotation. It does but only when using the built in 2d accelerator to do the rendering. if writing an image to the display it needs to be software rotated. The statement is not entirely correct.

I work on the LVGL project specifically the binding to MicroPython. My goal is to have the display drivers written in Python and the different display busses done in C using the esp_lcd component. That all works and the bus drivers are exposed to MicroPython in a "pythonic" way. The reason why I decided to go that route is to make the display drivers loadable at runtime instead of compile time. So a user is able to unplug a display, plug a different one in, change some lines of code and they are off and running again. No need to compile and flash firmware. This greatly reduces development time for the user.

This current display is some kind of a frankenstein that was made. It is an edge case scenario but I can see this kind of a thing needing to be used with the ESP32 because of the lack of MIPI support with the ESP32. MIPI is going to be gaining traction because of its low pin requirement and also it's speed. RGB is not really the most ideal bus for an ESP32 because of the large number of pins but also the lack of GRAM in the display means the display would need to have the buffer data written at a pretty fast rate. I8080, SPI and I2C are the best ways to connect. So an IC like this is going to need to be used to make that possible. I think it's a good thing they used the display IC they used because it will offer faster rendering due to the built in 2d accelerator. Need to extend LVGL to be able to use that rendered. I have to dig into what the capabilities are of the renderer, if it can do things like gradients and such. It does handle font rendering but I do not know how that works yet.

It's still not working.

I have a 100amp 5v power supply attached so I know there is no issue with power. I am using an ESP32-S3 N32R8 Octal RAM and flash. It's a devkit made by Espressif, it's not some junk board from Amazon.

Here is the logs you wanted.

ESP-ROM:esp32s3-20210327
Build:Mar 27 2021
rst:0x1 (POWERON),boot:0x38 (SPI_FAST_FLASH_BOOT)
SPIWP:0xee
Octal Flash Mode Enabled
For OPI Flash, Use Default Flash Boot Mode
mode:SLOW_RD, clock div:1
load:0x3fce3818,len:0x23d8
load:0x403c9700,len:0x4
load:0x403c9704,len:0xfac
load:0x403cc700,len:0x3578
entry 0x403c9980
I (37) boot: ESP-IDF v5.1.2 2nd stage bootloader
I (37) boot: compile time Dec 29 2023 19:39:20
I (37) boot: Multicore bootloader
D (40) bootloader_flash: non-XMC chip detected by SFDP Read (87), skip.
D (47) bootloader_flash: mmu set block paddr=0x00000000 (was 0xffffffff)
I (54) boot: chip revision: v0.1
D (58) boot.esp32s3: magic e9
D (61) boot.esp32s3: segments 04
D (64) boot.esp32s3: spi_mode 02
D (67) boot.esp32s3: spi_speed 0f
D (71) boot.esp32s3: spi_size 05
I (74) boot.esp32s3: Boot SPI Speed : 80MHz
I (79) boot.esp32s3: SPI Mode       : SLOW READ
I (84) boot.esp32s3: SPI Flash Size : 32MB
D (89) boot: Enabling RTCWDT(9000 ms)
I (92) boot: Enabling RNG early entropy source...
D (98) bootloader_flash: rodata starts from paddr=0x00008000, size=0xc00, will be mapped to vaddr=0x3c000000
V (108) bootloader_flash: after mapping, starting from paddr=0x00000000 and vaddr=0x3c000000, 0x10000 bytes are mapped
D (118) boot: mapped partition table 0x8000 at 0x3c008000
D (124) flash_parts: partition table verified, 5 entries
I (129) boot: Partition Table:
I (133) boot: ## Label            Usage          Type ST Offset   Length
D (140) boot: load partition table entry 0x3c008000
D (145) boot: type=1 subtype=2
I (149) boot:  0 nvs              WiFi data        01 02 00009000 00006000
D (156) boot: load partition table entry 0x3c008020
D (161) boot: type=1 subtype=1
I (164) boot:  1 phy_init         RF data          01 01 0000f000 00001000
D (172) boot: load partition table entry 0x3c008040
D (177) boot: type=0 subtype=0
I (180) boot:  2 factory          factory app      00 00 00010000 0026f000
D (187) boot: load partition table entry 0x3c008060
D (192) boot: type=1 subtype=81
I (195) boot:  3 vfs              Unknown data     01 81 0027f000 01d81000
I (203) boot: End of partition table
D (207) boot: Trying partition index -1 offs 0x10000 size 0x26f000
D (214) esp_image: reading image header @ 0x10000
D (218) bootloader_flash: mmu set block paddr=0x00010000 (was 0xffffffff)
D (225) esp_image: image header: 0xe9 0x07 0x02 0x05 40376688
V (231) esp_image: loading segment header 0 at offset 0x10018
V (237) esp_image: segment data length 0x7cd04 data starts 0x10020
V (243) esp_image: segment 0 map_segment 1 segment_data_offs 0x10020 load_addr 0x3c1e0020
I (251) esp_image: segment 0: paddr=00010020 vaddr=3c1e0020 size=7cd04h (511236) map
D (260) esp_image: free data page_count 0x00000200
D (265) bootloader_flash: rodata starts from paddr=0x00010020, size=0x7cd04, will be mapped to vaddr=0x3c000000
V (275) bootloader_flash: after mapping, starting from paddr=0x00010000 and vaddr=0x3c000000, 0x80000 bytes are mapped
V (409) esp_image: loading segment header 1 at offset 0x8cd24
D (409) bootloader_flash: mmu set block paddr=0x00080000 (was 0xffffffff)
V (410) esp_image: segment data length 0x32ec data starts 0x8cd2c
V (416) esp_image: segment 1 map_segment 0 segment_data_offs 0x8cd2c load_addr 0x3fc9f200
I (424) esp_image: segment 1: paddr=0008cd2c vaddr=3fc9f200 size=032ech ( 13036) load
D (433) esp_image: free data page_count 0x00000200
D (438) bootloader_flash: rodata starts from paddr=0x0008cd2c, size=0x32ec, will be mapped to vaddr=0x3c000000
V (448) bootloader_flash: after mapping, starting from paddr=0x00080000 and vaddr=0x3c000000, 0x20000 bytes are mapped
V (462) esp_image: loading segment header 2 at offset 0x90018
D (464) bootloader_flash: mmu set block paddr=0x00090000 (was 0xffffffff)
V (471) esp_image: segment data length 0x1d0280 data starts 0x90020
V (478) esp_image: segment 2 map_segment 1 segment_data_offs 0x90020 load_addr 0x42000020
I (486) esp_image: segment 2: paddr=00090020 vaddr=42000020 size=1d0280h (1901184) map
D (494) esp_image: free data page_count 0x00000200
D (499) bootloader_flash: rodata starts from paddr=0x00090020, size=0x1d0280, will be mapped to vaddr=0x3c000000
V (510) bootloader_flash: after mapping, starting from paddr=0x00090000 and vaddr=0x3c000000, 0x1e0000 bytes are mapped
V (978) esp_image: loading segment header 3 at offset 0x2602a0
D (978) bootloader_flash: mmu set block paddr=0x00260000 (was 0xffffffff)
V (979) esp_image: segment data length 0x29b4 data starts 0x2602a8
V (985) esp_image: segment 3 map_segment 0 segment_data_offs 0x2602a8 load_addr 0x3fca24ec
I (994) esp_image: segment 3: paddr=002602a8 vaddr=3fca24ec size=029b4h ( 10676) load
D (1002) esp_image: free data page_count 0x00000200
D (1007) bootloader_flash: rodata starts from paddr=0x002602a8, size=0x29b4, will be mapped to vaddr=0x3c000000
V (1017) bootloader_flash: after mapping, starting from paddr=0x00260000 and vaddr=0x3c000000, 0x10000 bytes are mapped
V (1031) esp_image: loading segment header 4 at offset 0x262c5c
D (1034) bootloader_flash: mmu set block paddr=0x00260000 (was 0xffffffff)
V (1041) esp_image: segment data length 0x1b154 data starts 0x262c64
V (1048) esp_image: segment 4 map_segment 0 segment_data_offs 0x262c64 load_addr 0x40374000
I (1056) esp_image: segment 4: paddr=00262c64 vaddr=40374000 size=1b154h (110932) load
D (1065) esp_image: free data page_count 0x00000200
D (1070) bootloader_flash: rodata starts from paddr=0x00262c64, size=0x1b154, will be mapped to vaddr=0x3c000000
V (1080) bootloader_flash: after mapping, starting from paddr=0x00260000 and vaddr=0x3c000000, 0x20000 bytes are mapped
V (1122) esp_image: loading segment header 5 at offset 0x27ddb8
D (1122) bootloader_flash: mmu set block paddr=0x00270000 (was 0xffffffff)
V (1124) esp_image: segment data length 0x808 data starts 0x27ddc0
V (1130) esp_image: segment 5 map_segment 0 segment_data_offs 0x27ddc0 load_addr 0x500007f8
I (1138) esp_image: segment 5: paddr=0027ddc0 vaddr=500007f8 size=00808h (  2056) load
D (1147) esp_image: free data page_count 0x00000200
D (1152) bootloader_flash: rodata starts from paddr=0x0027ddc0, size=0x808, will be mapped to vaddr=0x3c000000
V (1162) bootloader_flash: after mapping, starting from paddr=0x00270000 and vaddr=0x3c000000, 0x10000 bytes are mapped
V (1174) esp_image: loading segment header 6 at offset 0x27e5c8
D (1179) bootloader_flash: mmu set block paddr=0x00270000 (was 0xffffffff)
V (1186) esp_image: segment data length 0x3c data starts 0x27e5d0
V (1192) esp_image: segment 6 map_segment 0 segment_data_offs 0x27e5d0 load_addr 0x600fe000
I (1200) esp_image: segment 6: paddr=0027e5d0 vaddr=600fe000 size=0003ch (    60) load
D (1209) esp_image: free data page_count 0x00000200
D (1214) bootloader_flash: rodata starts from paddr=0x0027e5d0, size=0x3c, will be mapped to vaddr=0x3c000000
V (1224) bootloader_flash: after mapping, starting from paddr=0x00270000 and vaddr=0x3c000000, 0x10000 bytes are mapped
V (1235) esp_image: image start 0x00010000 end of last section 0x0027e60c
D (1242) bootloader_flash: mmu set block paddr=0x00270000 (was 0xffffffff)
D (1249) boot: Calculated hash: 64ac8a90e2fe979de685c1b7f33aea7db7c0360b5f2da409b31937aca88ee546
I (1269) boot: Loaded app from partition at offset 0x10000
I (1269) boot: Disabling RNG early entropy source...
D (1270) boot: Mapping segment 0 as DROM
D (1274) boot: Mapping segment 2 as IROM
D (1278) boot: calling set_cache_and_start_app
D (1282) boot: configure drom and irom and start
V (1287) boot: rodata starts from paddr=0x00010020, vaddr=0x3c1e0020, size=0x7cd04
V (1294) boot: after mapping rodata, starting from paddr=0x00010000 and vaddr=0x3c1e0000, 0x80000 bytes are mapped
V (1305) boot: text starts from paddr=0x00090020, vaddr=0x42000020, size=0x1d0280
V (1312) boot: after mapping text, starting from paddr=0x00090000 and vaddr=0x42000000, 0x1e0000 bytes are mapped
D (1323) boot: start: 0x40376688
I (1337) cpu_start: Multicore app
V (1338) mmap: after coalescing, 1 regions are left
I (1338) octal_psram: vendor id    : 0x0d (AP)
I (1340) octal_psram: dev id       : 0x02 (generation 3)
I (1346) octal_psram: density      : 0x03 (64 Mbit)
I (1352) octal_psram: good-die     : 0x01 (Pass)
I (1357) octal_psram: Latency      : 0x01 (Fixed)
I (1362) octal_psram: VCC          : 0x00 (1.8V)
I (1368) octal_psram: SRF          : 0x01 (Fast Refresh)
I (1374) octal_psram: BurstType    : 0x01 (Hybrid Wrap)
I (1379) octal_psram: BurstLen     : 0x01 (32 Byte)
I (1385) octal_psram: Readlatency  : 0x02 (10 cycles@Fixed)
I (1391) octal_psram: DriveStrength: 0x00 (1/1)
D (1397) MSPI Timing: 0, good
D (1400) MSPI Timing: 1, good
D (1403) MSPI Timing: 2, bad
D (1406) MSPI Timing: 3, good
D (1409) MSPI Timing: 4, good
D (1412) MSPI Timing: 5, good
D (1415) MSPI Timing: 6, good
D (1418) MSPI Timing: 7, good
D (1421) MSPI Timing: 8, bad
D (1424) MSPI Timing: 9, good
D (1427) MSPI Timing: 10, good
D (1430) MSPI Timing: 11, good
D (1433) MSPI Timing: 12, good
D (1436) MSPI Timing: 13, good
D (1439) MSPI Timing: tuning success, best point is index 5
I (1445) MSPI Timing: PSRAM timing tuning index: 5
I (1450) esp_psram: Found 8MB PSRAM device
I (1455) esp_psram: Speed: 80MHz
V (1459) mmap: found laddr is 0x260000
V (1463) esp_psram: 8bit-aligned-region: actual_mapped_len is 0x800000 bytes
V (1470) esp_psram: 8bit-aligned-range: 0x800000 B, starting from: 0x3c260000
I (1477) cpu_start: Pro cpu up.
I (1481) cpu_start: Starting app cpu, entry point is 0x4037656c
I (0) cpu_start: App cpu up.
V CACHE_ERR: illegal error intr clr & ena mask is: 0x3f
V CACHE_ERR: core 1 access error intr clr & ena mask is: 0x1f
I (1901) esp_psram: SPI SRAM memory test OK
D (1909) clk: RTC_SLOW_CLK calibration value: 3668301
V CACHE_ERR: illegal error intr clr & ena mask is: 0x3f
V CACHE_ERR: core 0 access error intr clr & ena mask is: 0x1f
I (1914) cpu_start: Pro cpu start user code
I (1918) cpu_start: cpu freq: 240000000 Hz
I (1923) cpu_start: Application information:
I (1928) cpu_start: Compile time:     Dec 29 2023 19:39:03
I (1934) cpu_start: ELF file SHA256:  8b0d4e914f326609...
I (1940) cpu_start: ESP-IDF:          v5.1.2
I (1945) cpu_start: Min chip rev:     v0.0
I (1950) cpu_start: Max chip rev:     v0.99
I (1955) cpu_start: Chip rev:         v0.1
V (1960) memory_layout: reserved range is 0x3c25ccdc - 0x3c25cd0c
D (1966) memory_layout: Checking 7 reserved memory ranges:
D (1971) memory_layout: Reserved memory range 0x3c000000 - 0x3e000000
D (1978) memory_layout: Reserved memory range 0x3fc84000 - 0x3fc9f200
D (1984) memory_layout: Reserved memory range 0x3fc9f200 - 0x3fcac200
D (1991) memory_layout: Reserved memory range 0x3fceee34 - 0x3fcf0000
D (1997) memory_layout: Reserved memory range 0x40374000 - 0x4038f200
D (2004) memory_layout: Reserved memory range 0x600fe000 - 0x600fe03c
D (2010) memory_layout: Reserved memory range 0x600fffd8 - 0x60100000
D (2017) memory_layout: Building list of available memory regions:
V (2023) memory_layout: Examining memory region 0x3c000000 - 0x3e000000
V (2030) memory_layout: Region 0x3c000000 - 0x3e000000 inside of reserved 0x3c000000 - 0x3e000000
V (2039) memory_layout: Examining memory region 0x40374000 - 0x40378000
V (2045) memory_layout: Region 0x40374000 - 0x40378000 inside of reserved 0x40374000 - 0x4038f200
V (2054) memory_layout: Examining memory region 0x3fc88000 - 0x3fc90000
V (2061) memory_layout: Region 0x3fc88000 - 0x3fc90000 inside of reserved 0x3fc84000 - 0x3fc9f200
V (2070) memory_layout: Examining memory region 0x3fc90000 - 0x3fca0000
V (2077) memory_layout: Start of region 0x3fc90000 - 0x3fca0000 overlaps reserved 0x3fc84000 - 0x3fc9f200
V (2086) memory_layout: Region 0x3fc9f200 - 0x3fca0000 inside of reserved 0x3fc9f200 - 0x3fcac200
V (2095) memory_layout: Examining memory region 0x3fca0000 - 0x3fcb0000
V (2102) memory_layout: Start of region 0x3fca0000 - 0x3fcb0000 overlaps reserved 0x3fc9f200 - 0x3fcac200
D (2112) memory_layout: Available memory region 0x3fcac200 - 0x3fcb0000
V (2118) memory_layout: Examining memory region 0x3fcb0000 - 0x3fcc0000
D (2125) memory_layout: Available memory region 0x3fcb0000 - 0x3fcc0000
V (2132) memory_layout: Examining memory region 0x3fcc0000 - 0x3fcd0000
D (2138) memory_layout: Available memory region 0x3fcc0000 - 0x3fcd0000
V (2145) memory_layout: Examining memory region 0x3fcd0000 - 0x3fce0000
D (2152) memory_layout: Available memory region 0x3fcd0000 - 0x3fce0000
V (2158) memory_layout: Examining memory region 0x3fce0000 - 0x3fce9710
D (2165) memory_layout: Available memory region 0x3fce0000 - 0x3fce9710
V (2172) memory_layout: Examining memory region 0x3fce9710 - 0x3fcf0000
V (2178) memory_layout: End of region 0x3fce9710 - 0x3fcf0000 overlaps reserved 0x3fceee34 - 0x3fcf0000
D (2188) memory_layout: Available memory region 0x3fce9710 - 0x3fceee34
V (2195) memory_layout: Examining memory region 0x3fcf0000 - 0x3fcf8000
D (2201) memory_layout: Available memory region 0x3fcf0000 - 0x3fcf8000
V (2208) memory_layout: Examining memory region 0x600fe000 - 0x60100000
V (2215) memory_layout: Start of region 0x600fe000 - 0x60100000 overlaps reserved 0x600fe000 - 0x600fe03c
V (2224) memory_layout: End of region 0x600fe03c - 0x60100000 overlaps reserved 0x600fffd8 - 0x60100000
D (2234) memory_layout: Available memory region 0x600fe03c - 0x600fffd8
I (2240) heap_init: Initializing. RAM available for dynamic allocation:
D (2248) heap_init: New heap initialised at 0x3fcac200
I (2253) heap_init: At 3FCAC200 len 0003D510 (245 KiB): D/IRAM
I (2259) heap_init: At 3FCE9710 len 00005724 (21 KiB): STACK/DIRAM
D (2266) heap_init: New heap initialised at 0x3fcf0000
I (2271) heap_init: At 3FCF0000 len 00008000 (32 KiB): DRAM
D (2278) heap_init: New heap initialised at 0x600fe03c
I (2283) heap_init: At 600FE03C len 00001F9C (7 KiB): RTCRAM
I (2289) esp_psram: Adding pool of 8192K of PSRAM memory to heap allocator
V (2297) intr_alloc: esp_intr_alloc_intrstatus (cpu 0): checking args
V (2303) intr_alloc: esp_intr_alloc_intrstatus (cpu 0): Args okay. Resulting flags 0x40E
D (2312) intr_alloc: Connected src 39 to int 2 (cpu 0)
W (2317) spi_flash: Octal flash chip is using but qio mode is selected, will automatically swich to Octal mode
D (2327) spi_flash: trying chip: issi
D (2331) spi_flash: trying chip: gd
D (2335) spi_flash: trying chip: mxic
D (2338) spi_flash: trying chip: winbond
D (2342) spi_flash: trying chip: boya
D (2346) spi_flash: trying chip: th
D (2350) spi_flash: trying chip: mxic (opi)
I (2354) spi_flash: detected chip: mxic (opi)
I (2359) spi_flash: flash io: opi_str
D (2363) cpu_start: calling init function: 0x421a9868
D (2369) cpu_start: calling init function: 0x421a9348
D (2374) cpu_start: calling init function: 0x42159630
D (2379) cpu_start: calling init function: 0x42131424
D (2384) cpu_start: calling init function: 0x4212996c
W (2389) rmt(legacy): legacy driver is deprecated, please migrate to `driver/rmt_tx.h` and/or `driver/rmt_rx.h`
D (2400) cpu_start: calling init function: 0x4212715c
W (2405) i2s(legacy): legacy i2s driver is deprecated, please migrate to use driver/i2s_std.h, driver/i2s_pdm.h or driver/i2s_tdm.h
D (2417) cpu_start: calling init function: 0x421256ac
D (2423) efuse: In EFUSE_BLK2__DATA4_REG is used 2 bits starting with 0 bit
D (2429) efuse: In EFUSE_BLK2__DATA4_REG is used 8 bits starting with 21 bit
D (2437) efuse: In EFUSE_BLK2__DATA4_REG is used 3 bits starting with 29 bit
D (2444) efuse: In EFUSE_BLK2__DATA5_REG is used 3 bits starting with 0 bit
D (2451) efuse: In EFUSE_BLK2__DATA5_REG is used 6 bits starting with 3 bit
D (2458) efuse: In EFUSE_BLK2__DATA5_REG is used 6 bits starting with 9 bit
V (2465) adc_share_hw_ctrl: Calib(V1) ADC1 atten=0: 07B8
D (2470) efuse: In EFUSE_BLK2__DATA4_REG is used 2 bits starting with 0 bit
D (2477) efuse: In EFUSE_BLK2__DATA4_REG is used 8 bits starting with 21 bit
D (2484) efuse: In EFUSE_BLK2__DATA4_REG is used 3 bits starting with 29 bit
D (2491) efuse: In EFUSE_BLK2__DATA5_REG is used 3 bits starting with 0 bit
D (2498) efuse: In EFUSE_BLK2__DATA5_REG is used 6 bits starting with 3 bit
D (2505) efuse: In EFUSE_BLK2__DATA5_REG is used 6 bits starting with 9 bit
V (2513) adc_share_hw_ctrl: Calib(V1) ADC1 atten=1: 0839
D (2518) efuse: In EFUSE_BLK2__DATA4_REG is used 2 bits starting with 0 bit
D (2525) efuse: In EFUSE_BLK2__DATA4_REG is used 8 bits starting with 21 bit
D (2532) efuse: In EFUSE_BLK2__DATA4_REG is used 3 bits starting with 29 bit
D (2539) efuse: In EFUSE_BLK2__DATA5_REG is used 3 bits starting with 0 bit
D (2546) efuse: In EFUSE_BLK2__DATA5_REG is used 6 bits starting with 3 bit
D (2553) efuse: In EFUSE_BLK2__DATA5_REG is used 6 bits starting with 9 bit
V (2560) adc_share_hw_ctrl: Calib(V1) ADC1 atten=2: 0853
D (2566) efuse: In EFUSE_BLK2__DATA4_REG is used 2 bits starting with 0 bit
D (2573) efuse: In EFUSE_BLK2__DATA4_REG is used 8 bits starting with 21 bit
D (2580) efuse: In EFUSE_BLK2__DATA4_REG is used 3 bits starting with 29 bit
D (2587) efuse: In EFUSE_BLK2__DATA5_REG is used 3 bits starting with 0 bit
D (2594) efuse: In EFUSE_BLK2__DATA5_REG is used 6 bits starting with 3 bit
D (2601) efuse: In EFUSE_BLK2__DATA5_REG is used 6 bits starting with 9 bit
V (2608) adc_share_hw_ctrl: Calib(V1) ADC1 atten=3: 08B8
D (2613) efuse: In EFUSE_BLK2__DATA4_REG is used 2 bits starting with 0 bit
D (2620) efuse: In EFUSE_BLK2__DATA5_REG is used 8 bits starting with 15 bit
D (2628) efuse: In EFUSE_BLK2__DATA5_REG is used 6 bits starting with 23 bit
D (2635) efuse: In EFUSE_BLK2__DATA5_REG is used 3 bits starting with 29 bit
D (2642) efuse: In EFUSE_BLK2__DATA6_REG is used 3 bits starting with 0 bit
D (2649) efuse: In EFUSE_BLK2__DATA6_REG is used 6 bits starting with 3 bit
V (2656) adc_share_hw_ctrl: Calib(V1) ADC2 atten=0: 0894
D (2661) efuse: In EFUSE_BLK2__DATA4_REG is used 2 bits starting with 0 bit
D (2668) efuse: In EFUSE_BLK2__DATA5_REG is used 8 bits starting with 15 bit
D (2675) efuse: In EFUSE_BLK2__DATA5_REG is used 6 bits starting with 23 bit
D (2682) efuse: In EFUSE_BLK2__DATA5_REG is used 3 bits starting with 29 bit
D (2690) efuse: In EFUSE_BLK2__DATA6_REG is used 3 bits starting with 0 bit
D (2697) efuse: In EFUSE_BLK2__DATA6_REG is used 6 bits starting with 3 bit
V (2704) adc_share_hw_ctrl: Calib(V1) ADC2 atten=1: 08B9
D (2709) efuse: In EFUSE_BLK2__DATA4_REG is used 2 bits starting with 0 bit
D (2716) efuse: In EFUSE_BLK2__DATA5_REG is used 8 bits starting with 15 bit
D (2723) efuse: In EFUSE_BLK2__DATA5_REG is used 6 bits starting with 23 bit
D (2730) efuse: In EFUSE_BLK2__DATA5_REG is used 3 bits starting with 29 bit
D (2737) efuse: In EFUSE_BLK2__DATA6_REG is used 3 bits starting with 0 bit
D (2744) efuse: In EFUSE_BLK2__DATA6_REG is used 6 bits starting with 3 bit
V (2751) adc_share_hw_ctrl: Calib(V1) ADC2 atten=2: 08C9
D (2757) efuse: In EFUSE_BLK2__DATA4_REG is used 2 bits starting with 0 bit
D (2764) efuse: In EFUSE_BLK2__DATA5_REG is used 8 bits starting with 15 bit
D (2771) efuse: In EFUSE_BLK2__DATA5_REG is used 6 bits starting with 23 bit
D (2778) efuse: In EFUSE_BLK2__DATA5_REG is used 3 bits starting with 29 bit
D (2785) efuse: In EFUSE_BLK2__DATA6_REG is used 3 bits starting with 0 bit
D (2792) efuse: In EFUSE_BLK2__DATA6_REG is used 6 bits starting with 3 bit
V (2799) adc_share_hw_ctrl: Calib(V1) ADC2 atten=3: 08E3
D (2805) cpu_start: calling init function: 0x42125668
W (2810) ADC: legacy driver is deprecated, please migrate to `esp_adc/adc_oneshot.h`
D (2818) cpu_start: calling init function: 0x420af478
D (2824) cpu_start: calling init function: 0x420af06c
D (2829) cpu_start: calling init function: 0x420b4dfc on core: 0
V (2835) intr_alloc: esp_intr_alloc_intrstatus (cpu 0): checking args
V (2841) intr_alloc: esp_intr_alloc_intrstatus (cpu 0): Args okay. Resulting flags 0xC02
D (2849) intr_alloc: Connected src 59 to int 3 (cpu 0)
D (2854) cpu_start: calling init function: 0x420b25b4 on core: 0
I (2861) sleep: Configure to isolate all GPIO pins in sleep state
I (2867) sleep: Enable automatic switching of GPIO sleep configuration
D (2874) cpu_start: calling init function: 0x420b0234 on core: 0
I (2892) coexist: coex firmware version: b6d5e8c
I (2892) coexist: coexist rom version e7ae62f
V (2892) intr_alloc: esp_intr_alloc_intrstatus (cpu 0): checking args
V (2898) intr_alloc: esp_intr_alloc_intrstatus (cpu 0): Args okay. Resulting flags 0x40E
D (2906) intr_alloc: Connected src 79 to int 9 (cpu 0)
I (2911) app_start: Starting scheduler on CPU0
V (2916) intr_alloc: esp_intr_alloc_intrstatus (cpu 0): checking args
V (2916) intr_alloc: esp_intr_alloc_intrstatus (cpu 0): Args okay. Resulting flags 0x402
D (2916) intr_alloc: Connected src 57 to int 12 (cpu 0)
V (2916) intr_alloc: esp_intr_alloc_intrstatus (cpu 1): checking args
V (2926) intr_alloc: esp_intr_alloc_intrstatus (cpu 1): Args okay. Resulting flags 0x40E
D (2926) intr_alloc: Connected src 80 to int 2 (cpu 1)
I (2936) app_start: Starting scheduler on CPU1
V (2936) intr_alloc: esp_intr_alloc_intrstatus (cpu 1): checking args
V (2946) intr_alloc: esp_intr_alloc_intrstatus (cpu 1): Args okay. Resulting flags 0x402
D (2956) intr_alloc: Connected src 58 to int 3 (cpu 1)
I (2916) main_task: Started on CPU0
D (2966) heap_init: New heap initialised at 0x3fce9710
I (2966) esp_psram: Reserving pool of 32K of internal memory for DMA/internal allocations
D (2976) esp_psram: Allocating block of size 32768 bytes
V (2986) intr_alloc: esp_intr_alloc_intrstatus (cpu 0): checking args
V (2986) intr_alloc: esp_intr_alloc_intrstatus (cpu 0): Args okay. Resulting flags 0xE
D (2996) intr_alloc: Connected src 52 to int 13 (cpu 0)
I (3006) main_task: Calling app_main()
V (3006) partition: Loading the partition table
V (3016) mmap: actual_mapped_len is 0x10000
V (3016) calculated md5: 0x3fcf3848   eb e1 e2 2c a9 03 70 cc  fc fa 50 da e1 19 32 fe  |...,..p...P...2.|
V (3026) stored md5: 0x3ca68090   eb e1 e2 2c a9 03 70 cc  fc fa 50 da e1 19 32 fe  |...,..p...P...2.|
V (3036) partition: Partition table MD5 verified
I (3046) main_task: Returned from app_main()
W (3046) TinyUSB: The device's configuration descriptor is not provided by user, using default.
W (3056) TinyUSB: The device's string descriptor is not provided by user, using default.
W (3066) TinyUSB: The device's device descriptor is not provided by user, using default.
I (3076) tusb_desc:
┌─────────────────────────────────┐
│  USB Device Descriptor Summary  │
├───────────────────┬─────────────┤
│bDeviceClass       │ 239         │
├───────────────────┼─────────────┤
│bDeviceSubClass    │ 2           │
├───────────────────┼─────────────┤
│bDeviceProtocol    │ 1           │
├───────────────────┼─────────────┤
│bMaxPacketSize0    │ 64          │
├───────────────────┼─────────────┤
│idVendor           │ 0x303a      │
├───────────────────┼─────────────┤
│idProduct          │ 0x4001      │
├───────────────────┼─────────────┤
│bcdDevice          │ 0x100       │
├───────────────────┼─────────────┤
│iManufacturer      │ 0x1         │
├───────────────────┼─────────────┤
│iProduct           │ 0x2         │
├───────────────────┼─────────────┤
│iSerialNumber      │ 0x3         │
├───────────────────┼─────────────┤
│bNumConfigurations │ 0x1         │
└───────────────────┴─────────────┘
V (3246) intr_alloc: esp_intr_alloc_intrstatus (cpu 1): checking args
V (3246) intr_alloc: esp_intr_alloc_intrstatus (cpu 1): Args okay. Resulting flags 0xE
D (3256) intr_alloc: Connected src 38 to int 4 (cpu 1)
D (3266) tusb_tsk: tinyusb task started
I (3266) TinyUSB: TinyUSB Driver installed
D (3266) tusb_cdc:▒RB▒▒²JJ▒▒▒}▒▒▒▒▒▒ esp_intr_alloc_intrstatus (cpu 1): checking args
V (3286) intr_alloc: esp_intr_alloc_intrstatus (cpu 1): Args okay. Resulting flags 0x40E
D (3286) intr_alloc: Connected src 27 to int 9 (cpu 1)
D (3296) event: created task for loop 0x3fcee53c
D (3296) event: running task for loop 0x3fcee53c
D (3296) event: created event loop 0x3fcee53c
V (3306) intr_alloc: esp_intr_alloc_intrstatus (cpu 1): checking args
V (3316) intr_alloc: esp_intr_alloc_intrstatus (cpu 1): Args okay. Resulting flags 0xE
D (3316) intr_alloc: Connected src 16 to int 12 (cpu 1)
V (3326) spi_flash: allocate temp buffer: 0x3fcee978 (32)
V (3326) spi_flash: allocate temp buffer: 0x3fcee978 (32)
V (3336) spi_flash: allocate temp buffer: 0x3fcee978 (128)
V (3346) spi_flash: allocate temp buffer: 0x3fcee978 (128)
V (3346) spi_flash: allocate temp buffer: 0x3fcee978 (32)
V (3356) spi_flash: allocate temp buffer: 0x3fcee978 (32)
V (3356) spi_flash: allocate temp buffer: 0x3fcee978 (32)
V (3366) spi_flash: allocate temp buffer: 0x3fcee978 (32)
V (3366) spi_flash: allocate temp buffer: 0x3fcee978 (32)
V (3376) spi_flash: allocate temp buffer: 0x3fcee978 (32)
V (3376) spi_flash: allocate temp buffer: 0x3fcee978 (32)
V (3386) spi_flash: allocate temp buffer: 0x3fcee978 (32)
V (3396) spi_flash: allocate temp buffer: 0x3fcee978 (32)
V (3396) spi_flash: allocate temp buffer: 0x3fcee978 (32)
V (3406) spi_flash: allocate temp buffer: 0x3fcee978 (32)
V (3406) spi_flash: allocate temp buffer: 0x3fcee978 (32)
V (3416) spi_flash: allocate temp buffer: 0x3fcee978 (32)
V (3416) spi_flash: allocate temp buffer: 0x3fcee978 (128)
V (3426) spi_flash: allocate temp buffer: 0x3fcee978 (128)
V (3426) spi_flash: allocate temp buffer: 0x3fcee978 (32)
V (3436) spi_flash: allocate temp buffer: 0x3fcee978 (32)
V (3436) spi_flash: allocate temp buffer: 0x3fcee978 (32)
V (3446) spi_flash: allocate temp buffer: 0x3fcee978 (32)
V (3456) spi_flash: allocate temp buffer: 0x3fcee978 (32)
V (3456) spi_flash: allocate temp buffer: 0x3fceea28 (32)
V (3466) spi_flash: allocate temp buffer: 0x3fceea28 (32)
V (3466) spi_flash: allocate temp buffer: 0x3fceea28 (128)
V (3476) spi_flash: allocate temp buffer: 0x3fceea28 (128)
V (3476) spi_flash: allocate temp buffer: 0x3fceea28 (32)
V (3486) spi_flash: allocate temp buffer: 0x3fceea28 (32)
V (3486) spi_flash: allocate temp buffer: 0x3fceea28 (32)
V (3496) spi_flash: allocate temp buffer: 0x3fceea28 (32)
V (3496) spi_flash: allocate temp buffer: 0x3fceea28 (128)
V (3506) spi_flash: allocate temp buffer: 0x3fceea28 (128)
V (3516) spi_flash: allocate temp buffer: 0x3fceea28 (32)
V (3516) spi_flash: allocate temp buffer: 0x3fceea28 (32)
V (3526) spi_flash: allocate temp buffer: 0x3fceea28 (128)
V (3526) spi_flash: allocate temp buffer: 0x3fceea28 (128)
MicroPython v1.21.0-dirty on 2023-12-29; Generic ESP32S3 module with Octal-SPIRAM with ESP32S3
Type "help()" for more information.
>>> import test
V (16756) spi_flash: allocate temp buffer: 0x3fceea28 (32)
V (16756) spi_flash: allocate temp buffer: 0x3fceea28 (32)
V (16756) spi_flash: allocate temp buffer: 0x3fceea28 (128)
V (16766) spi_flash: allocate temp buffer: 0x3fceea28 (128)
V (16766) spi_flash: allocate temp buffer: 0x3fceea28 (32)
V (16776) spi_flash: allocate temp buffer: 0x3fceea28 (32)
V (16776) spi_flash: allocate temp buffer: 0x3fceea28 (128)
V (16786) spi_flash: allocate temp buffer: 0x3fceea28 (128)
V (16796) spi_flash: allocate temp buffer: 0x3fceea28 (32)
V (16796) spi_flash: allocate temp buffer: 0x3fceea28 (32)
V (16806) spi_flash: allocate temp buffer: 0x3fceea28 (128)
V (16806) spi_flash: allocate temp buffer: 0x3fceea28 (128)
V (16816) spi_flash: allocate temp buffer: 0x3fceea28 (128)
V (16816) spi_flash: allocate temp buffer: 0x3fceea28 (128)
V (16826) spi_flash: allocate temp buffer: 0x3fceea28 (128)
V (16836) spi_flash: allocate temp buffer: 0x3fceea28 (128)
V (16836) spi_flash: allocate temp buffer: 0x3fceea28 (128)
V (16846) spi_flash: allocate temp buffer: 0x3fceea28 (128)
V (16846) spi_flash: allocate temp buffer: 0x3fceea28 (128)
V (16856) spi_flash: allocate temp buffer: 0x3fceea28 (128)
V (16856) spi_flash: allocate temp buffer: 0x3fceea28 (128)
V (16866) spi_flash: allocate temp buffer: 0x3fceea28 (128)
V (16876) spi_flash: allocate temp buffer: 0x3fceea28 (128)
V (16876) spi_flash: allocate temp buffer: 0x3fceea28 (128)
V (16886) spi_flash: allocate temp buffer: 0x3fceea28 (128)
V (16886) spi_flash: allocate temp buffer: 0x3fceea28 (128)
V (16896) spi_flash: allocate temp buffer: 0x3fceea28 (128)
V (16896) spi_flash: allocate temp buffer: 0x3fceea28 (128)
V (16906) spi_flash: allocate temp buffer: 0x3fceea28 (128)
V (16906) spi_flash: allocate temp buffer: 0x3fceea28 (128)
V (16916) spi_flash: allocate temp buffer: 0x3fceea28 (128)
V (16926) spi_flash: allocate temp buffer: 0x3fceea28 (128)
V (16926) spi_flash: allocate temp buffer: 0x3fceea28 (128)
V (16936) spi_flash: allocate temp buffer: 0x3fceea28 (128)
V (16936) spi_flash: allocate temp buffer: 0x3fceea28 (128)
V (16946) spi_flash: allocate temp buffer: 0x3fceea28 (128)
V (16946) spi_flash: allocate temp buffer: 0x3fceea28 (128)
V (16956) spi_flash: allocate temp buffer: 0x3fceea28 (128)
V (16966) spi_flash: allocate temp buffer: 0x3fceea28 (128)
V (16966) spi_flash: allocate temp buffer: 0x3fceea28 (128)
V (16976) spi_flash: allocate temp buffer: 0x3fceea28 (128)
V (16986) spi_flash: allocate temp buffer: 0x3fceea28 (32)
V (16986) spi_flash: allocate temp buffer: 0x3fceea28 (32)
V (16986) spi_flash: allocate temp buffer: 0x3fceea28 (128)
V (16996) spi_flash: allocate temp buffer: 0x3fceea28 (128)
V (16996) spi_flash: allocate temp buffer: 0x3fceea28 (32)
V (17006) spi_flash: allocate temp buffer: 0x3fceea28 (32)
V (17006) spi_flash: allocate temp buffer: 0x3fceea28 (128)
V (17016) spi_flash: allocate temp buffer: 0x3fceea28 (128)
V (17026) spi_flash: allocate temp buffer: 0x3fceea28 (32)
V (17026) spi_flash: allocate temp buffer: 0x3fceea28 (32)
V (17036) spi_flash: allocate temp buffer: 0x3fceea28 (128)
V (17036) spi_flash: allocate temp buffer: 0x3fceea28 (128)
V (17046) spi_flash: allocate temp buffer: 0x3fceea28 (32)
V (17046) spi_flash: allocate temp buffer: 0x3fceea28 (32)
V (17056) spi_flash: allocate temp buffer: 0x3fceea28 (128)
V (17056) spi_flash: allocate temp buffer: 0x3fceea28 (128)
V (17066) spi_flash: allocate temp buffer: 0x3fceea28 (32)
V (17076) spi_flash: allocate temp buffer: 0x3fceea28 (32)
V (17076) spi_flash: allocate temp buffer: 0x3fceea28 (128)
V (17086) spi_flash: allocate temp buffer: 0x3fceea28 (128)
V (17086) spi_flash: allocate temp buffer: 0x3fceea28 (32)
V (17096) spi_flash: allocate temp buffer: 0x3fceea28 (32)
V (17096) spi_flash: allocate temp buffer: 0x3fceea28 (128)
V (17106) spi_flash: allocate temp buffer: 0x3fceea28 (128)
I (17116) gpio: GPIO[2]| InputEn: 0| OutputEn: 1| OpenDrain: 0| Pullup: 1| Pulldown: 0| Intr:0
I (17116) gpio: GPIO[1]| InputEn: 0| OutputEn: 1| OpenDrain: 0| Pullup: 1| Pulldown: 0| Intr:0
I (17126) gpio: GPIO[21]| InputEn: 0| OutputEn: 1| OpenDrain: 0| Pullup: 1| Pulldown: 0| Intr:0
I (17136) gpio: GPIO[0]| InputEn: 0| OutputEn: 1| OpenDrain: 0| Pullup: 1| Pulldown: 0| Intr:0
I (17326) gpio: GPIO[2]| InputEn: 0| OutputEn: 0| OpenDrain: 0| Pullup: 1| Pulldown: 0| Intr:0
I (17326) gpio: GPIO[1]| InputEn: 0| OutputEn: 0| OpenDrain: 0| Pullup: 1| Pulldown: 0| Intr:0
ra8876.RA8875
display.init
V (17346) intr_alloc: esp_intr_alloc_intrstatus (cpu 1): checking args
V (17346) intr_alloc: esp_intr_alloc_intrstatus (cpu 1): Args okay. Resulting flags 0x90E
D (17356) intr_alloc: Connected src 24 to int 13 (cpu 1)
D (17356) gdma: new group (0) at 0x3c270ac4
D (17366) gdma: new pair (0,0) at 0x3c270b08
D (17366) gdma: new tx channel (0,0) at 0x3c270a90
D (17366) gdma: tx channel (0,0), (0:32) bytes aligned, burst enabled
D (17376) lcd_panel.io.i80: new i80 bus(0) @0x3fcac940, 26 dma nodes
D (17386) lcd_panel.io.i80: new i80 lcd panel io @0x3c270b28 on bus(0)
I (17386) gpio: GPIO[39]| InputEn: 0| OutputEn: 1| OpenDrain: 0| Pullup: 0| Pulldown: 0| Intr:0
I (17396) gpio: GPIO[40]| InputEn: 1| OutputEn: 0| OpenDrain: 0| Pullup: 1| Pulldown: 0| Intr:0
D (17406) ra8876: new ra8876 panel @0x3fceebb4
lv.display_create
set_color_format
set_flush_cb
set_draw_buffers
screen_active
set_style_bg_color
slider
set_size
center
V (17846) spi_flash: allocate temp buffer: 0x3fceec08 (32)
V (17846) spi_flash: allocate temp buffer: 0x3fceec08 (32)
V (17846) spi_flash: allocate temp buffer: 0x3fceec08 (128)
V (17856) spi_flash: allocate temp buffer: 0x3fceec08 (128)
V (17856) spi_flash: allocate temp buffer: 0x3fceec08 (32)
V (17866) spi_flash: allocate temp buffer: 0x3fceec08 (32)
V (17866) spi_flash: allocate temp buffer: 0x3fceec08 (128)
V (17876) spi_flash: allocate temp buffer: 0x3fceec08 (128)
V (17886) spi_flash: allocate temp buffer: 0x3fceec08 (32)
V (17886) spi_flash: allocate temp buffer: 0x3fceec08 (32)
V (17896) spi_flash: allocate temp buffer: 0x3fceec08 (128)
V (17896) spi_flash: allocate temp buffer: 0x3fceec08 (128)
V (17906) spi_flash: allocate temp buffer: 0x3fceec08 (32)
V (17906) spi_flash: allocate temp buffer: 0x3fceec08 (32)
V (17916) spi_flash: allocate temp buffer: 0x3fceec08 (128)
V (17926) spi_flash: allocate temp buffer: 0x3fceec08 (128)
V (17926) spi_flash: allocate temp buffer: 0x3fceec08 (32)
V (17936) spi_flash: allocate temp buffer: 0x3fceec08 (32)
V (17936) spi_flash: allocate temp buffer: 0x3fceec08 (128)
V (17946) spi_flash: allocate temp buffer: 0x3fceec08 (128)
V (17946) spi_flash: allocate temp buffer: 0x3fceec08 (32)
V (17956) spi_flash: allocate temp buffer: 0x3fceec08 (32)
V (17956) spi_flash: allocate temp buffer: 0x3fceec08 (128)
V (17966) spi_flash: allocate temp buffer: 0x3fceec08 (128)
flush called
flush called
flush called
flush called
flush called
flush called
flush called
flush called
flush called
flush called

You should look at getting a flame scallop for your tank. They are actually really cool. They are electroluminescence.

I don't have it any more but I put together a 44 gallon tall pentagon tank, 10 gallon sump using a fluidized bed instead of bio balls, protein skimmer, metal-halide with VHO actinics. I don't remember off hand what the weight of the live rock was that I had in the tank. It was completely full from top to bottom. Crushed coral base. I ended up moving to the other side of the country (USA) and I had no way of moving the tank. I ended up giving it away. Sad day that was. I had to give away 2 tanks. I had a 20 gallon fresh that was almost 100% self sustaining. I didn't have to feed the fish at all. I only added water and cleaned the impeller on the filter when it stopped turning. Occasionally I would have to go in and trim back the amazon broad leaf that was in the tank. It would grow to the point where 1/2 of it would be sticking out of the top of the tank.

Maybe I will get another tank going at some point. I have always wanted to do a 300 gallon or larger and have a drip system that would keep the water level where it should be. I am on well water now so none of the funky chemicals added by the town/city.

You will also appreciate this.

The hole in the rack has been filled with 4 HTPC machines I built. I have a 6 tuner network attached cable TV tuner and I ran HDMI cables to the locations where the TV's are. ESP32's are used to pass IR remote signals to a main server and that is what controls the various devices in my house. The main server takes care of the lights, locks, security cameras and also holds the database of all of my movies and video games.

5000 VA APC modified so it has a 24 hour runtime at 80% load. The bottom of the rack is 4 telecom batteries. the batteries fill the entire width and depth of the rack 48cm wide x 68cm deep x 45cm tall.

IMG_20221111_152332

32 core AMD Threadripper Pro with 128GB of RAM. Supermicro machine. supports up to 2TB or RAM, Has a 2000 watt power supply. 4 NVMe SSD sockets on the mainboard. IPMI. All the goodies normally seen in a server.

IMG_20230807_211732

I have been looking at the code for your component and I am not sure how it was working. I have not gotten it working yet as I am still going over the parameters being sent to the display. From what I am seeing in the data sheet some of the registers are being set in the wrong order and things like the external SDRAM are disabled (which makes setting the SDRAM timings pointless to do). The output TFT bit depth is set to 16 when it should be set to 24.

There is no reason to do a hard reset before doing a soft reset.

The soft reset command is incorrect You have this as the soft reset

    esp_lcd_panel_io_tx_param(ra8876->io, RA8876_REG_SRR, (uint8_t[]) { 0x01 }, 1);

You are only telling the chip to reset, you are not telling it that you want to change the PLL values,

This is from the data sheet for bit 7

Reconfigure PLL frequency Write “1” to this bit will reconfigure PLL frequency. Note:

When user change PLL relative parameters, PLL clock won‟t change immediately, user must set this bit as “1” again.

User may read (check) this bit to know whether system already switch to PLL clock or not yet.

So bit 7 has to be set to a 1 and bit 0 has to be set to 1 to perform the reset to reconfigure the PLL. Then once the PLL has been reconfigured bit 7 has to be set to a 1 once again and bit 0 gets set to a zero.

You have this line

    esp_lcd_panel_io_tx_param(ra8876->io, RA8876_REG_CCR, (uint8_t[]) { ra8876->chip_config_register }, 1);

which is setting the CCR register to 0x40. If you read the data sheet bit 1 turns on and off the Serial flash (SDRAM). so you have it turned off by default. Setting the SDRAM timings are not necessary to do. That command also has bit 7 which is listed as a read write bit but it only mentions reading from that bit to see if the PLL has changed. I do not know if any off behavior will occur by setting this bit to a zero if it has been set to a 1. Since the RD line is not connected there is no way to read data from the display. So a safe bet would be to place this before you make the PLL changes so that when the bit does get set you are not having to modify it at all.

The other thing that register controls is the host bus width. Bit 0 does this. a value of 0 for bit 0 is 8 bit bus and a value of 1 is 16 bit bus. so setting this register to 0x40 sets the bus width to 8 bits not 16. this needs to be set to 0x41 prior to setting the PLL

I am still working on the registers to see what is out of alignment. The code given in the examples from buydisplay always assume that the display has the SDRAM. for my display it is an optional thing but adding one is not given as an option so it needs to be disabled.

Their example code is very poorly written and it makes assumptions. IDK if you based you code off those examples or not but I can understand why you have things the way they are if you did. I sent them an e-mail blasting them about the pins and also about the code examples being incorrect. I highly doubt their examples work properly, no way of knowing unless the same MCU they used is purchased. Not going to do that. ST's SDK is junk. It looks like it was thrown together and I can't make heads or tails of how to use it. There are so many different pieces of software involved to get it to work. too much of a headache to learn it.

Hi,

I used their code plus some others from online to gather something together that worked for me.

The driver code works on an ER-TFTM070-6 screen from buydisplay in 16-bit 8080 mode, which is the one I have here that I tested it against.

This is my init code for that panel using my driver if it helps...

I have CS and RD pins permanently tied to reduce my pin usage on the ESP32S3. I'm clocking at 16MHz (the highest I could get with stable display output on my board design) and using 16-bit colour depth as RGB565 is so much easier to deal with in LVGL.

--snip-- esp_lcd_i80_bus_handle_t i80_bus = NULL; esp_lcd_i80_bus_config_t bus_config = { .clk_src = LCD_CLK_SRC_PLL160M, .dc_gpio_num = LCD_DC, .wr_gpio_num = LCD_WR, .data_gpio_nums = { LCD_D0, LCD_D1, LCD_D2, LCD_D3, LCD_D4, LCD_D5, LCD_D6, LCD_D7, LCD_D8, LCD_D9, LCD_D10, LCD_D11, LCD_D12, LCD_D13, LCD_D14, LCD_D15 }, .bus_width = 16, .psram_trans_align = 64, .sram_trans_align = 4, .max_transfer_bytes = 1024 20 sizeof(uint16_t) }; esp_lcd_new_i80_bus(&bus_config, &i80_bus); esp_lcd_panel_io_handle_t io_handle = NULL; esp_lcd_panel_io_i80_config_t io_config = { .cs_gpio_num = GPIO_NUM_NC, .pclk_hz = (16 1000 1000), .trans_queue_depth = 32, .dc_levels = { .dc_idle_level = 0, .dc_cmd_level = 0, .dc_dummy_level = 0, .dc_data_level = 1, }, .flags = { .swap_color_bytes = 0, .pclk_idle_low = 0, }, .on_color_trans_done = _notify_lvgl_flush_ready, .user_ctx = &disp_drv, .lcd_cmd_bits = 16, .lcd_param_bits = 8, }; esp_lcd_new_panel_io_i80(i80_bus, &io_config, &io_handle); const esp_lcd_panel_ra8876_config_t vendor_config = { .wait_gpio_num = LCD_WAIT, .lcd_width = 1024, .lcd_height = 600, .mcu_bit_interface = 16, }; esp_lcd_panel_dev_config_t panel_config = { .reset_gpio_num = LCD_RST, .color_space = ESP_LCD_COLOR_SPACE_RGB, .bits_per_pixel = 16, .vendor_config = (void*)&vendor_config, .flags = { .reset_active_high = 0, } }; esp_lcd_new_panel_ra8876(io_handle, &panel_config, &lcd_panel_handle); esp_lcd_panel_init(lcd_panel_handle); esp_lcd_panel_disp_on_off(lcd_panel_handle, true); esp_lcd_panel_set_backlight(lcd_panel_handle, 25); // 25% // configure backlight ledc_fade_func_install(0); ledc_timer_config_t ledc_timer = { .speed_mode = LEDC_LOW_SPEED_MODE, .timer_num = LEDC_TIMER_1, .duty_resolution = LEDC_TIMER_8_BIT, .freq_hz = 5000, .clk_cfg = LEDC_AUTO_CLK }; ledc_timer_config(&ledc_timer); ledc_channel_config_t ledc_channel = { .speed_mode = LEDC_LOW_SPEED_MODE, .channel = LEDC_CHANNEL_1, .timer_sel = LEDC_TIMER_1, .intr_type = LEDC_INTR_DISABLE, .gpio_num = LCD_BL, .duty = 0, .hpoint = 0 }; ledc_channel_config(&ledc_channel); // set backlight to 20% (51) ledc_set_duty_and_update(LEDC_LOW_SPEED_MODE, LEDC_CHANNEL_1, 51, 0); --snip--

Hope that helps.

On 31/12/2023 19:09, Kevin Schlosser wrote:

I have been looking at the code for your component and I am not sure how it was working. I have not gotten it working yet as I am still going over the parameters being sent to the display. From what I am seeing in the data sheet some of the registers are being set in the wrong order and things like the external SDRAM are disabled (which makes setting the SDRAM timings pointless to do). The output TFT bit depth is set to 16 when it should be set to 24.

There is no reason to do a hard reset before doing a soft reset.

The soft reset command is incorrect You have this as the soft reset

esp_lcd_panel_io_tx_param(ra8876->io,RA8876_REG_SRR, (uint8_t[]) {0x01 },1);

You are only telling the chip to reset, you are not telling it that you want to change the PLL values,

This is from the data sheet for bit 7
Reconfigure PLL frequency
Write “1” to this bit will reconfigure PLL frequency.
Note:

 1. When user change PLL relative parameters, PLL clock won‟t
    change immediately, user must set this bit as “1” again.
 2. User may read (check) this bit to know whether system already
    switch to PLL clock or not yet.
So bit 7 has to be set to a 1 and bit 0 has to be set to 1 to perform the reset to reconfigure the PLL. Then once the PLL has been reconfigured bit 7 has to be set to a 1 once again and bit 0 gets set to a zero.

You have this line

esp_lcd_panel_io_tx_param(ra8876->io,RA8876_REG_CCR, (uint8_t[]) {ra8876->chip_config_register },1);

which is setting the CCR register to 0x40. If you read the data sheet bit 1 turns on and off the Serial flash (SDRAM). so you have it turned off by default. Setting the SDRAM timings are not necessary to do. That command also has bit 7 which is listed as a read write bit but it only mentions reading from that bit to see if the PLL has changed. I do not know if any off behavior will occur by setting this bit to a zero if it has been set to a 1. Since the RD line is not connected there is no way to read data from the display. So a safe bet would be to place this before you make the PLL changes so that when the bit does get set you are not having to modify it at all.

The other thing that register controls is the host bus width. Bit 0 does this. a value of 0 for bit 0 is 8 bit bus and a value of 1 is 16 bit bus. so setting this register to 0x40 sets the bus width to 8 bits not

this needs to be set to 0x41 prior to setting the PLL

I am still working on the registers to see what is out of alignment. The code given in the examples from buydisplay always assume that the display has the SDRAM. for my display it is an optional thing but adding one is not given as an option so it needs to be disabled.

Their example code is very poorly written and it makes assumptions. IDK if you based you code off those examples or not but I can understand why you have things the way they are if you did. I sent them an e-mail blasting them about the pins and also about the code examples being incorrect. I highly doubt their examples work properly, no way of knowing unless the same MCU they used is purchased. Not going to do that. ST's SDK is junk. It looks like it was thrown together and I can't make heads or tails of how to use it. There are so many different pieces of software involved to get it to work. too much of a headache to learn it.

— Reply to this email directly, view it on GitHub https://github.com/danmeuk/esp_lcd_ra8876/issues/1#issuecomment-1873019071, or unsubscribe https://github.com/notifications/unsubscribe-auth/AELHMSX3QZ4ZIBIAT2LHSHTYMGZ5VAVCNFSM6AAAAABBF2WGUWVHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHMYTQNZTGAYTSMBXGE. You are receiving this because you commented.Message ID: @.***>

Things are changing in LVGL V9. it has native support of 24 bit color. There is no longer a need to compile it with the color depth set. It now gets set at runtime instead of compile time. swapping the byte order when using RGB565 is no longer done using a macro. there is an additional function that you would call inside the flush function to handle this stuff.

I am one of the guys that works on LVGL :smile:

I am working on the MicroPython binding and getting that all squared away so it supports the latest ESP IDF and cleaned up the build code so it is now a separate entity instead of needing to change 1/2 the build system to compile the binding. It can be dropped in and no files need to be changed in the MicroPython build system for it to work.

I have opened up a dialog with the head developer about adding renderer support for this display IC. It is always going to be faster for things to get rendered using the display IC vs rendering to a display buffer and having to send the buffer to the display. Now I know how the display IC works is by writing to it's internal GRAM and then sending that to the display but the connection between the display IC and the panel it's self is a 24 lane RGB connection that is running at a lot faster speed than the I8080 is. There are a lot of rendering functions available in this display so may as well use them to do as much rendering as possible to get the absolute best performance from it.

Expect to see something for it in LVGL hopefully sooner than later. I think after we finish up getting V9 released and get the initial bugs cleaned up in there will be more time to spend on stuff like adding the code to use this display IC to it's potential.

I have not seen what the actual display IC output looks like what it does the rendering. I am hoping it isn't complete shit, LOL. hate to waste my time to find out that it doesn't have support for things like antialiasing which I haven't come across in the data sheet at all. I didn't go looking either.

These display IC's have almost too many settings and features. There is such a thing as too much flexibility and I am pretty sure this IC fits into that group.

There are difference between the 2 displays with the front and back porch settings and also the pulse width settings. There are a couple others as well.

HSCAN_L_to_R is not used for mine but This would not cause a problem

my display - your display PCLK_Rising - PCLK_Falling HSYNC_Low_Active - HSYNC_High_Active VSYNC_Low_Active - VSYNC_High_Active

danmeuk / esp_lcd_ra8876

I am not able to get this component to work at all. #1