Page 44 of the RISC-V ISA mandates "The quotient of division by zero has all bits set, and the remainder of division by zero equals the dividend."
Our checker fails showing that the updates did not happen in cycle 38 to the register 7 in response to a prior remu instruction detected in cycle 37. x[5] is divided by x[7] and x[7] is 0 and rd is 7. We expect x[7] to be same as x[5] but it isn't.
Page 44 of the RISC-V ISA mandates "The quotient of division by zero has all bits set, and the remainder of division by zero equals the dividend."
Our checker fails showing that the updates did not happen in cycle 38 to the register 7 in response to a prior remu instruction detected in cycle 37. x[5] is divided by x[7] and x[7] is 0 and rd is 7. We expect x[7] to be same as x[5] but it isn't.