The RISC-V ISA mandates that if the target address is not 4-byte aligned then the exception must be raised. The check on byte-alignment is on the target address not the target offset. The RTL is doing this on the target offset. Hence, JAL target address check fails.
For reference the spec we have used is the 2019 version of the base ISA. The exact specification lines are recorded here for easy reference.
"The JAL and JALR instructions will generate an instruction-address-misaligned exception if the target address is not aligned to
a four-byte boundary."
There appears to be a fundamental issue with the processor design in that all references to PC for additions to immediate values happen to be on 30 bit values of PC rather than 32 bits (ISA requirement). This results in address computations for JAL, and other B-type instructions to yield incorrect address values.
The RISC-V ISA mandates that if the target address is not 4-byte aligned then the exception must be raised. The check on byte-alignment is on the target address not the target offset. The RTL is doing this on the target offset. Hence, JAL target address check fails.
For reference the spec we have used is the 2019 version of the base ISA. The exact specification lines are recorded here for easy reference. "The JAL and JALR instructions will generate an instruction-address-misaligned exception if the target address is not aligned to a four-byte boundary."
There appears to be a fundamental issue with the processor design in that all references to PC for additions to immediate values happen to be on 30 bit values of PC rather than 32 bits (ISA requirement). This results in address computations for JAL, and other B-type instructions to yield incorrect address values.
JAL_target_fail.vcd.gz