davidthings / tinyfpga_bx_usbserial

USB Serial on the TinyFPGA BX
Apache License 2.0
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Problems Building on Windows #3

Closed docsteer closed 5 years ago

docsteer commented 5 years ago

I am trying to build this in a Windows environment and I'm getting a failure with timing errors. For tools I am using: Yosys 0.9 (git sha1 1979e0b1, i686-w64-mingw32.static-g++ 5.5.0 -Os) nextpnr-ice40 -- Next Generation Place and Route (git sha1 cadbf42)

I get: Info: Max frequency for clock 'clk48mhz$glb_clk': 38.37 MHz (FAIL at 48.00 MHz)

Full output below. Let me know if you have ideas.. I'll see if I can try a Linux system instead.


C:\Develop\fpga\tinyfpga_bx_usbserial>make
icepll -i 16 -o 48 -m -f pll.v

F_PLLIN:    16.000 MHz (given)
F_PLLOUT:   48.000 MHz (requested)
F_PLLOUT:   48.000 MHz (achieved)

FEEDBACK: SIMPLE
F_PFD:   16.000 MHz
F_VCO:  768.000 MHz

DIVR:  0 (4'b0000)
DIVF: 47 (7'b0101111)
DIVQ:  4 (3'b100)

FILTER_RANGE: 1 (3'b001)

PLL configuration written to: pll.v
yosys -q -p 'synth_ice40 -top usbserial_tbx -json usbserial_tbx.json' usbserial_tbx.v usb/edge_detect.v usb/serial.v usb/usb_fs_in_arb.v usb/usb_fs_in_pe.v usb/usb_fs_out_arb.v usb/usb_fs_out_pe.v usb/usb_fs_pe.v usb/usb_fs_rx.v usb/usb_fs_tx_mux.v usb/usb_fs_tx.v usb/usb_reset_det.v usb/usb_serial_ctrl_ep.v usb/usb_uart_bridge_ep.v usb/usb_uart_core.v usb/usb_uart_i40.v pll.v
Warning: Replacing memory \ep_state_next with list of registers. See usb/usb_fs_in_pe.v:181
Warning: Replacing memory \ep_state with list of registers. See usb/usb_fs_in_pe.v:235, usb/usb_fs_in_pe.v:111
Warning: Replacing memory \ep_put_addr with list of registers. See usb/usb_fs_in_pe.v:243, usb/usb_fs_in_pe.v:109
Warning: Replacing memory \ep_get_addr with list of registers. See usb/usb_fs_out_pe.v:230
Warning: Replacing memory \ep_state with list of registers. See usb/usb_fs_out_pe.v:225
Warning: Replacing memory \ep_get_addr_next with list of registers. See usb/usb_fs_out_pe.v:213
Warning: Replacing memory \ep_state_next with list of registers. See usb/usb_fs_out_pe.v:158
Warning: Wire usbserial_tbx.uart.uart.ctrl_ep_inst.in_ep_data has an unprocessed 'init' attribute.
Warning: Wire usbserial_tbx.uart.uart.ctrl_ep_inst.send_zero_length_data_pkt has an unprocessed 'init' attribute.
Warning: Wire usbserial_tbx.uart.uart.ctrl_ep_inst.setup_stage_end has an unprocessed 'init' attribute.
Warning: Wire usbserial_tbx.uart.uart.ctrl_ep_inst.status_stage_end has an unprocessed 'init' attribute.
Warning: Wire usbserial_tbx.uart.uart.usb_fs_pe_inst.usb_fs_in_pe_inst.endp_free has an unprocessed 'init' attribute.
Warning: Wire usbserial_tbx.uart.uart.usb_fs_pe_inst.usb_fs_in_pe_inst.in_ep_acked has an unprocessed 'init' attribute.
Warning: Wire usbserial_tbx.uart.uart.usb_fs_pe_inst.usb_fs_in_pe_inst.in_ep_data_free has an unprocessed 'init' attribute.
Warning: Wire usbserial_tbx.uart.uart.usb_fs_pe_inst.usb_fs_in_pe_inst.in_ep_num has an unprocessed 'init' attribute.
Warning: Wire usbserial_tbx.uart.uart.usb_fs_pe_inst.usb_fs_in_pe_inst.in_xfr_end has an unprocessed 'init' attribute.
Warning: Wire usbserial_tbx.uart.uart.usb_fs_pe_inst.usb_fs_in_pe_inst.tx_pid has an unprocessed 'init' attribute.
Warning: Wire usbserial_tbx.uart.uart.usb_fs_pe_inst.usb_fs_in_pe_inst.tx_pkt_start has an unprocessed 'init' attribute.
Warning: Wire usbserial_tbx.uart.uart.usb_fs_pe_inst.usb_fs_out_pe_inst.new_pkt_end has an unprocessed 'init' attribute.
Warning: Wire usbserial_tbx.uart.uart.usb_fs_pe_inst.usb_fs_out_pe_inst.out_ep_acked has an unprocessed 'init' attribute.
Warning: Wire usbserial_tbx.uart.uart.usb_fs_pe_inst.usb_fs_out_pe_inst.out_ep_num has an unprocessed 'init' attribute.
Warning: Wire usbserial_tbx.uart.uart.usb_fs_pe_inst.usb_fs_out_pe_inst.out_xfr_start has an unprocessed 'init' attribute.
Warning: Wire usbserial_tbx.uart.uart.usb_fs_pe_inst.usb_fs_out_pe_inst.rollback_data has an unprocessed 'init' attribute.
Warning: Wire usbserial_tbx.uart.uart.usb_fs_pe_inst.usb_fs_out_pe_inst.tx_pid has an unprocessed 'init' attribute.
Warning: Wire usbserial_tbx.uart.uart.usb_fs_pe_inst.usb_fs_out_pe_inst.tx_pkt_start has an unprocessed 'init' attribute.
nextpnr-ice40 --lp8k --freq 48 --package cm81 --pcf pins.pcf --json usbserial_tbx.json --asc usbserial_tbx.asc
Info: Importing module usbserial_tbx
Info: Rule checker, verifying imported design
Info: Checksum: 0x84317ea4

Info: constrained 'pin_led' to bel 'X5/Y33/io1'
Info: constrained 'pin_usb_p' to bel 'X9/Y33/io0'
Info: constrained 'pin_usb_n' to bel 'X10/Y33/io1'
Info: constrained 'pin_pu' to bel 'X6/Y33/io0'
Info: constrained 'pin_clk' to bel 'X0/Y30/io0'
Info: constrained 'debug[0]' to bel 'X33/Y2/io0'
Info: constrained 'debug[1]' to bel 'X33/Y6/io0'
Info: constrained 'debug[2]' to bel 'X33/Y17/io0'
Info: constrained 'debug[3]' to bel 'X33/Y21/io1'

Info: Packing constants..
Info: Packing IOs..
Info: pin_usb_p feeds SB_IO uart.iobuf_usbp, removing $nextpnr_iobuf pin_usb_p.
Info: pin_usb_n feeds SB_IO uart.iobuf_usbn, removing $nextpnr_iobuf pin_usb_n.
Info: Packing LUT-FFs..
Info: Packing non-LUT FFs..
Info: Packing carries..
Info: Packing RAMs..
Info: Placing PLLs..
Info:   constrained PLL 'pll48.uut' to X16/Y0/pll_3
Info: Packing special functions..
Info:   PLL 'pll48.uut' has LOCK output, need to pass all outputs via LUT
Info:   LUT strategy for LOCK: move all users to new LUT
Info:   constrained 'pll48.uut_PLL$nextpnr_LOCK_lut_through' to X1/Y1/lc0
Info: Promoting globals..
Info: promoting clk_48mhz (fanout 420)
Info: promoting debug[1] [reset] (fanout 96)
Info: promoting uart.uart.ctrl_ep_inst.status_stage_end [reset] (fanout 22)
Info: promoting $abc$17106$auto$rtlil.cc:1969:NotGate$16856 [reset] (fanout 21)
Info: promoting $abc$17106$auto$dff2dffe.cc:158:make_patterns_logic$15337 [cen] (fanout 32)
Info: promoting $abc$17106$auto$dff2dffe.cc:158:make_patterns_logic$14115 [cen] (fanout 21)
Info: promoting $abc$17106$auto$dff2dffe.cc:158:make_patterns_logic$15690 [cen] (fanout 16)
Info: Constraining chains...
Info: Checksum: 0x7fbd2419

Info: Annotating ports with timing budgets for target frequency 48.00 MHz
Info: Checksum: 0xf78a8325

Info: Device utilisation:
Info:            ICESTORM_LC:  1097/ 7680    14%
Info:           ICESTORM_RAM:     2/   32     6%
Info:                  SB_IO:     9/  256     3%
Info:                  SB_GB:     8/    8   100%
Info:           ICESTORM_PLL:     1/    2    50%
Info:            SB_WARMBOOT:     0/    1     0%

Info: Placed 12 cells based on constraints.
Info: Creating initial placement for remaining 1105 cells.
Info:   initial placement placed 500/1105 cells
Info:   initial placement placed 1000/1105 cells
Info:   initial placement placed 1105/1105 cells
Info: Initial placement time 0.53s
Info: Running simulated annealing placer.
Info:   at iteration #1: temp = 10000.000000, cost = 75251, est tns = -2032.34ns
Info:   at iteration #5: temp = 2401.000000, cost = 74778, est tns = -1988.36ns
Info:   at iteration #10: temp = 403.536072, cost = 73886, est tns = -2009.56ns
Info:   at iteration #15: temp = 197.732681, cost = 68588, est tns = -1835.67ns
Info:   at iteration #20: temp = 96.889008, cost = 63896, est tns = -1656.43ns
Info:   at iteration #25: temp = 87.200104, cost = 61297, est tns = -1685.13ns
Info:   at iteration #30: temp = 63.568878, cost = 61617, est tns = -1701.36ns
Info:   at iteration #35: temp = 57.211990, cost = 56935, est tns = -1490.42ns
Info:   at iteration #40: temp = 46.341713, cost = 55533, est tns = -1516.34ns
Info:   at iteration #45: temp = 44.024628, cost = 51292, est tns = -1273.06ns
Info:   at iteration #50: temp = 37.745613, cost = 50721, est tns = -1330.57ns
Info:   at iteration #55: temp = 34.065418, cost = 49390, est tns = -1264.61ns
Info:   at iteration #60: temp = 30.744041, cost = 45462, est tns = -1178.92ns
Info:   at iteration #65: temp = 27.746496, cost = 44155, est tns = -1100.88ns
Info:   at iteration #70: temp = 26.359171, cost = 41978, est tns = -1018.57ns
Info:   at iteration #75: temp = 25.041212, cost = 40939, est tns = -1045.54ns
Info:   at iteration #80: temp = 25.041212, cost = 40906, est tns = -1040.14ns
Info:   at iteration #85: temp = 25.041212, cost = 40936, est tns = -1015.08ns
Info:   at iteration #90: temp = 25.041212, cost = 40749, est tns = -1063.39ns
Info:   at iteration #95: temp = 23.789152, cost = 41015, est tns = -1023.97ns
Info:   at iteration #100: temp = 22.599695, cost = 36863, est tns = -912.34ns
Info:   at iteration #105: temp = 21.469711, cost = 36026, est tns = -890.22ns
Info:   at iteration #110: temp = 20.396225, cost = 34743, est tns = -859.85ns
Info:   at iteration #115: temp = 19.376413, cost = 34074, est tns = -826.46ns
Info:   at iteration #120: temp = 17.487213, cost = 32155, est tns = -754.72ns
Info:   at iteration #125: temp = 16.612852, cost = 32113, est tns = -788.36ns
Info:   at iteration #130: temp = 15.782209, cost = 30616, est tns = -722.49ns
Info:   at iteration #135: temp = 14.243444, cost = 29445, est tns = -730.72ns
Info:   at iteration #140: temp = 14.243444, cost = 27315, est tns = -672.67ns
Info:   at iteration #145: temp = 13.531272, cost = 25378, est tns = -603.60ns
Info:   at iteration #150: temp = 12.854709, cost = 24216, est tns = -570.34ns
Info:   at iteration #155: temp = 11.601375, cost = 23465, est tns = -537.44ns
Info:   at iteration #160: temp = 11.601375, cost = 22527, est tns = -482.60ns
Info:   at iteration #165: temp = 10.470241, cost = 21073, est tns = -499.75ns
Info:   at iteration #170: temp = 9.946729, cost = 19143, est tns = -474.79ns
Info:   at iteration #175: temp = 8.976923, cost = 18747, est tns = -451.92ns
Info:   at iteration #180: temp = 8.528077, cost = 18164, est tns = -473.78ns
Info:   at iteration #185: temp = 8.101673, cost = 17043, est tns = -418.84ns
Info:   at iteration #190: temp = 7.696589, cost = 16222, est tns = -392.39ns
Info:   at iteration #195: temp = 6.946172, cost = 15574, est tns = -381.85ns
Info:   at iteration #200: temp = 6.598863, cost = 15410, est tns = -377.85ns
Info:   at iteration #205: temp = 6.268920, cost = 13753, est tns = -365.21ns
Info:   at iteration #210: temp = 5.657700, cost = 13142, est tns = -327.59ns
Info:   at iteration #215: temp = 5.374815, cost = 12636, est tns = -319.11ns
Info:   at iteration #220: temp = 5.106074, cost = 12443, est tns = -332.50ns
Info:   at iteration #225: temp = 4.850770, cost = 11157, est tns = -303.81ns
Info:   at iteration #230: temp = 4.377820, cost = 10366, est tns = -288.64ns
Info:   at iteration #235: temp = 4.158929, cost = 9864, est tns = -285.32ns
Info:   at iteration #240: temp = 3.950983, cost = 9576, est tns = -273.30ns
Info:   at iteration #245: temp = 3.565762, cost = 9088, est tns = -254.24ns
Info:   at iteration #250: temp = 3.565762, cost = 8502, est tns = -220.61ns
Info:   at iteration #255: temp = 3.057195, cost = 8388, est tns = -233.57ns
Info:   at iteration #260: temp = 2.904335, cost = 7973, est tns = -223.97ns
Info:   at iteration #265: temp = 2.759119, cost = 7449, est tns = -209.61ns
Info:   at iteration #270: temp = 2.621163, cost = 7164, est tns = -201.52ns
Info:   at iteration #275: temp = 2.365599, cost = 6756, est tns = -191.53ns
Info:   at iteration #280: temp = 2.134953, cost = 6394, est tns = -196.55ns
Info:   at iteration #285: temp = 1.707963, cost = 5790, est tns = -178.86ns
Info:   at iteration #290: temp = 1.707963, cost = 5577, est tns = -172.47ns
Info:   at iteration #295: temp = 1.366370, cost = 5093, est tns = -158.37ns
Info:   at iteration #300: temp = 1.093096, cost = 4847, est tns = -158.88ns
Info: Legalising relative constraints...
Info:     moved 5 cells, 4 unplaced (after legalising chains)
Info:        average distance 2.000000
Info:        maximum distance 2.000000
Info:     moved 9 cells, 0 unplaced (after replacing ripped up cells)
Info:        average distance 1.555556
Info:        maximum distance 2.000000
Info:   at iteration #305: temp = 10.000000, cost = 4684, est tns = -153.00ns
Info:   at iteration #310: temp = 9.025000, cost = 17838, est tns = -412.99ns
Info:   at iteration #315: temp = 6.983373, cost = 14581, est tns = -370.33ns
Info:   at iteration #320: temp = 5.688001, cost = 12306, est tns = -297.27ns
Info:   at iteration #325: temp = 4.632912, cost = 10713, est tns = -259.27ns
Info:   at iteration #330: temp = 3.584859, cost = 9281, est tns = -240.16ns
Info:   at iteration #335: temp = 2.919890, cost = 8142, est tns = -223.34ns
Info:   at iteration #340: temp = 2.259355, cost = 7001, est tns = -206.28ns
Info:   at iteration #345: temp = 1.748246, cost = 6208, est tns = -189.84ns
Info:   at iteration #350: temp = 0.680277, cost = 4880, est tns = -174.03ns
Info:   at iteration #355: temp = 0.544222, cost = 4312, est tns = -164.81ns
Info:   at iteration #360: temp = 0.435378, cost = 4197, est tns = -162.56ns
Info:   at iteration #365: temp = 0.222913, cost = 4104, est tns = -162.09ns
Info:   at iteration #370: temp = 0.073044, cost = 4072, est tns = -162.08ns
Info:   at iteration #375: temp = 0.029919, cost = 4056, est tns = -158.65ns
Info:   at iteration #380: temp = 0.009804, cost = 4048, est tns = -160.43ns
Info:   at iteration #385: temp = 0.003213, cost = 4042, est tns = -156.78ns
Info:   at iteration #390: temp = 0.001053, cost = 4042, est tns = -160.53ns
Info:   at iteration #395: temp = 0.000345, cost = 4039, est tns = -160.22ns
Info:   at iteration #399: temp = 0.000141, cost = 4039.000000
Info: SA placement time 7.84s

Info: Max frequency for clock 'clk_48mhz_$glb_clk': 38.37 MHz (FAIL at 48.00 MHz)

Info: Max delay <async>                    -> posedge clk_48mhz_$glb_clk: 3.03 ns
Info: Max delay posedge clk_48mhz_$glb_clk -> <async>                   : 7.59 ns

Info: Slack histogram:
Info:  legend: * represents 4 endpoint(s)
Info:          + represents [1,4) endpoint(s)
Info: [ -5231,  -4015) |***+
Info: [ -4015,  -2799) |
Info: [ -2799,  -1583) |*+
Info: [ -1583,   -367) |****+
Info: [  -367,    849) |******************+
Info: [   849,   2065) |*************+
Info: [  2065,   3281) |****************+
Info: [  3281,   4497) |*****************+
Info: [  4497,   5713) |********+
Info: [  5713,   6929) |********+
Info: [  6929,   8145) |******+
Info: [  8145,   9361) |**********+
Info: [  9361,  10577) |******************************+
Info: [ 10577,  11793) |*************+
Info: [ 11793,  13009) |********+
Info: [ 13009,  14225) |****************************+
Info: [ 14225,  15441) |*******************+
Info: [ 15441,  16657) |**********+
Info: [ 16657,  17873) |*********************+
Info: [ 17873,  19089) |************************************************************
Info: Checksum: 0x0a542f37

Info: Routing..
Info: Setting up routing queue.
Info: Routing 3267 arcs.
Info:            |   (re-)routed arcs  |   delta    | remaining
Info:    IterCnt |  w/ripup   wo/ripup |  w/r  wo/r |      arcs
Info:       1000 |       44        955 |   44   955 |      2323
Info:       2000 |      143       1856 |   99   901 |      1442
Info:       3000 |      257       2742 |  114   886 |       600
Info:       3643 |      293       3350 |   36   608 |         0
Info: Routing complete.
Info: Route time 0.81s
Info: Checksum: 0x3d4a2e4e

Info: Critical path report for clock 'clk_48mhz_$glb_clk' (posedge -> posedge):
Info: curr total
Info:  0.8  0.8  Source $abc$17106$auto$blifparse.cc:492:parse_blif$17709_LC.O
Info:  1.3  2.1    Net uart.uart.usb_fs_pe_inst.usb_fs_rx_inst.crc16[15] budget 1.758000 ns (7,8) -> (9,8)
Info:                Sink $abc$17106$auto$blifparse.cc:492:parse_blif$17135_LC.I0
Info:  0.7  2.8  Source $abc$17106$auto$blifparse.cc:492:parse_blif$17135_LC.O
Info:  1.3  4.1    Net $abc$17106$new_n780_ budget 1.758000 ns (9,8) -> (7,8)
Info:                Sink $abc$17106$auto$blifparse.cc:492:parse_blif$17134_LC.I0
Info:  0.7  4.8  Source $abc$17106$auto$blifparse.cc:492:parse_blif$17134_LC.O
Info:  1.9  6.7    Net $abc$17106$new_n779_ budget 1.758000 ns (7,8) -> (11,10)
Info:                Sink $abc$17106$auto$blifparse.cc:492:parse_blif$17128_LC.I1
Info:  0.6  7.2  Source $abc$17106$auto$blifparse.cc:492:parse_blif$17128_LC.O
Info:  2.3  9.6    Net $abc$17106$techmap\uart.uart.usb_fs_pe_inst.usb_fs_out_pe_inst.$logic_not$usb/usb_fs_out_pe.v:129$1515_Y_new_inv_ budget 1.907000 ns (11,10) -> (16,11)
Info:                Sink $abc$17106$auto$blifparse.cc:492:parse_blif$17127_LC.I0
Info:  0.7 10.3  Source $abc$17106$auto$blifparse.cc:492:parse_blif$17127_LC.O
Info:  1.9 12.1    Net $abc$17106$new_n772_ budget 1.907000 ns (16,11) -> (18,15)
Info:                Sink $abc$17106$auto$blifparse.cc:492:parse_blif$17126_LC.I0
Info:  0.7 12.8  Source $abc$17106$auto$blifparse.cc:492:parse_blif$17126_LC.O
Info:  2.5 15.3    Net uart.uart.usb_fs_pe_inst.tx_pid[1] budget 1.907000 ns (18,15) -> (18,25)
Info:                Sink $abc$17106$auto$blifparse.cc:492:parse_blif$17404_LC.I3
Info:  0.5 15.8  Source $abc$17106$auto$blifparse.cc:492:parse_blif$17404_LC.O
Info:  3.8 19.6    Net $abc$17106$auto$dff2dffe.cc:158:make_patterns_logic$15690 budget 1.907000 ns (18,25) -> (16,0)
Info:                Sink $gbuf_$abc$17106$auto$dff2dffe.cc:158:make_patterns_logic$15690_$glb_ce.USER_SIGNAL_TO_GLOBAL_BUFFER
Info:  0.9 20.5  Source $gbuf_$abc$17106$auto$dff2dffe.cc:158:make_patterns_logic$15690_$glb_ce.GLOBAL_BUFFER_OUTPUT
Info:  0.9 21.4    Net $abc$17106$auto$dff2dffe.cc:158:make_patterns_logic$15690_$glb_ce budget 1.907000 ns (16,0) -> (22,24)
Info:                Sink $auto$simplemap.cc:420:simplemap_dff$8542_DFFLC.CEN
Info:  0.1 21.5  Setup $auto$simplemap.cc:420:simplemap_dff$8542_DFFLC.CEN
Info: 5.5 ns logic, 16.0 ns routing

Info: Critical path report for cross-domain path '<async>' -> 'posedge clk_48mhz_$glb_clk':
Info: curr total
Info:  0.0  0.0  Source uart.iobuf_usbp.D_IN_0
Info:  1.7  1.7    Net uart.usb_p_in budget 19.931999 ns (9,33) -> (9,27)
Info:                Sink $auto$simplemap.cc:420:simplemap_dff$7293_DFFLC.I0
Info:  0.7  2.4  Setup $auto$simplemap.cc:420:simplemap_dff$7293_DFFLC.I0
Info: 0.7 ns logic, 1.7 ns routing

Info: Critical path report for cross-domain path 'posedge clk_48mhz_$glb_clk' -> '<async>':
Info: curr total
Info:  0.8  0.8  Source $abc$17106$auto$blifparse.cc:492:parse_blif$17443_LC.O
Info:  2.3  3.1    Net uart.uart.usb_fs_pe_inst.usb_fs_in_pe_inst.ep_state[1][1] budget 2.360000 ns (20,12) -> (26,13)
Info:                Sink $abc$17106$auto$blifparse.cc:492:parse_blif$17294_LC.I0
Info:  0.7  3.8  Source $abc$17106$auto$blifparse.cc:492:parse_blif$17294_LC.O
Info:  0.9  4.7    Net $abc$17106$auto$simplemap.cc:309:simplemap_lut$8220_new_ budget 2.360000 ns (26,13) -> (27,13)
Info:                Sink $abc$17106$auto$blifparse.cc:492:parse_blif$17296_LC.I3
Info:  0.5  5.1  Source $abc$17106$auto$blifparse.cc:492:parse_blif$17296_LC.O
Info:  2.3  7.5    Net debug[2] budget 6.265000 ns (27,13) -> (33,17)
Info:                Sink debug[2]$sb_io.D_OUT_0
Info:  0.1  7.6  Setup debug[2]$sb_io.D_OUT_0
Info: 2.0 ns logic, 5.6 ns routing

ERROR: Max frequency for clock 'clk_48mhz_$glb_clk': 46.52 MHz (FAIL at 48.00 MHz)

Info: Max delay <async>                    -> posedge clk_48mhz_$glb_clk: 2.56 ns
Info: Max delay posedge clk_48mhz_$glb_clk -> <async>                   : 7.59 ns

Info: Slack histogram:
Info:  legend: * represents 4 endpoint(s)
Info:          + represents [1,4) endpoint(s)
Info: [  -661,    326) |****+
Info: [   326,   1313) |********+
Info: [  1313,   2300) |************+
Info: [  2300,   3287) |************+
Info: [  3287,   4274) |*********+
Info: [  4274,   5261) |*********************+
Info: [  5261,   6248) |*******+
Info: [  6248,   7235) |******+
Info: [  7235,   8222) |**************+
Info: [  8222,   9209) |****+
Info: [  9209,  10196) |************+
Info: [ 10196,  11183) |**********+
Info: [ 11183,  12170) |*******+
Info: [ 12170,  13157) |*************************************+
Info: [ 13157,  14144) |********************+
Info: [ 14144,  15131) |***************+
Info: [ 15131,  16118) |********+
Info: [ 16118,  17105) |**********+
Info: [ 17105,  18092) |*************+
Info: [ 18092,  19079) |************************************************************
0 warnings, 1 error
make: *** [Makefile:49: usbserial_tbx.asc] Error 1
davidthings commented 5 years ago

I haven't seen this particular critical path before. Next time I'm working in the codebase, I'll take a look.

I might be wrong, but I think the error line relevant to your failure is:

ERROR: Max frequency for clock 'clk_48mhz_$glb_clk': 46.52 MHz (FAIL at 48.00 MHz)

So it's a squeaker.

It's interesting to see that the bulk of the time being used is in the routing:

Info: 5.5 ns logic, 16.0 ns routing

You are building for the TinyFPGA BX (iCE40 LP8K), right? I've heard that other iCE40 chips are slower.

For now, you could try one of these:

Pretty sure you can get it running this way.