Closed docsteer closed 5 years ago
I haven't seen this particular critical path before. Next time I'm working in the codebase, I'll take a look.
I might be wrong, but I think the error line relevant to your failure is:
ERROR: Max frequency for clock 'clk_48mhz_$glb_clk': 46.52 MHz (FAIL at 48.00 MHz)
So it's a squeaker.
It's interesting to see that the bulk of the time being used is in the routing:
Info: 5.5 ns logic, 16.0 ns routing
You are building for the TinyFPGA BX (iCE40 LP8K), right? I've heard that other iCE40 chips are slower.
For now, you could try one of these:
make gui
. Sometime it does different things. And it's very pretty.Pretty sure you can get it running this way.
I am trying to build this in a Windows environment and I'm getting a failure with timing errors. For tools I am using: Yosys 0.9 (git sha1 1979e0b1, i686-w64-mingw32.static-g++ 5.5.0 -Os) nextpnr-ice40 -- Next Generation Place and Route (git sha1 cadbf42)
I get: Info: Max frequency for clock 'clk48mhz$glb_clk': 38.37 MHz (FAIL at 48.00 MHz)
Full output below. Let me know if you have ideas.. I'll see if I can try a Linux system instead.