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dawsonjon / Chips-2.0

FPGA Design Suite based on C to Verilog design flow.
www.pyandchips.org
MIT License
232 stars 47 forks source link

Differential clock #35

Closed micrenda closed 8 years ago

micrenda commented 8 years ago

I am trying to build a base example for VC707 board. My first issue is that I have a differential clock input clk_p clk_n. Which is the cleanest way to integrate with Chips-2.0?

dawsonjon commented 8 years ago

Hi,

Probably the best option is to create a wrapper in vhdl or verilog, that instances the Chips output. You can instance an IBUFGDS in the wrapper to convert the clock to single ended. This wrapper https://github.com/dawsonjon/Chips-Demo/blob/master/source/atlys.vhd is for a Spartan 6 card, so it will need some modifications, but it might be a good starting point, it has gigabit ethernet (GMII) and UART interfaces.

Good luck with your project. Let me know if you have any other questions.

Jon

On 8 October 2015 at 15:30, Michele Renda notifications@github.com wrote:

I am trying to build a base example for VC707 board. My first issue is that I have a differential clock input clk_p clk_n. Which is the cleanest way to integrate with Chips-2.0?

— Reply to this email directly or view it on GitHub https://github.com/dawsonjon/Chips-2.0/issues/35.

micrenda commented 8 years ago

Indeed I learned a bit more about the Chips-2.0 and it was very simply solved adding a VHDL instance:

ibufgds_inst : IBUFGDS port map (I => clk_p, IB => clk_n, O => s_clk);

Thank you very much

(This bug report can be closed)