Port the GMac to 10/100 MAC on LX9 microboard

[liubenyuan]

Hi,

How to port your GMac implementation to 10, 100 MAC ? I am using LX9 microboard, and want to give your implementation, as well as chips-2.0 a try !!

Thanks!

Liu benyuan

[dawsonjon]

You could use the nexys3 branch as a starting point, it uses 10/100 Ethernet but it only supports full-duplex mode. I created this in order to support the digilent nexys card which only has 10/100 ethernet. I haven't tested it on a Nexys 3 card because I don't have one, it did work fine on the atlys card both at 10 and 100 Mbit/s though.

Since the LX 9 provides a 100 MHz clock, usb-uart and phy with MII interface, it should be as simple as editing the .ucf file to match the new pinout, and editing the build script (nexys3.py) to match the LX9 part number. I hope the design fits!

Thanks Jon

[liubenyuan]

Hi, I got a Nexys3 board from my pals, and burn the precompiled/NEXYS3.bit to board.

Then I config the ethernet via

sudo ip addr add 192.168.1.0/24 dev enp0s25


#turn off window scaling and timestamps
sudo sysctl -w net.ipv4.tcp_window_scaling=0
sudo sysctl -w net.ipv4.tcp_timestamps=0

However, when I ping by

$ ping 192.168.1.1
PING 192.168.1.1 (192.168.1.1) 56(84) bytes of data.
From 192.168.1.0 icmp_seq=1 Destination Host Unreachable
From 192.168.1.0 icmp_seq=2 Destination Host Unreachable
From 192.168.1.0 icmp_seq=3 Destination Host Unreachable
^C
--- 192.168.1.1 ping statistics ---
4 packets transmitted, 0 received, +3 errors, 100% packet loss, time 3008ms
pipe 4

Any suggestions ? 


[dawsonjon]

Your Ethernet configuration is a little different than mine. Not sure what difference this would make.

As I mentioned, I do not have a Nexys3 card myself, so I cannot guarantee that it will work. Amer Al-Canaan has managed to get this working in a NEXYS3, but he had to make some changes. I think the problem was the polarity of the reset that was incorrect. I have updated the precompiled demo with this change.

[liubenyuan]

Hi, great news, I am using your last updated .bit file, and it works! any detailed changes you have made to this bit file ?

BTW, the latency might be a little bit large, and there are occasionally packet loss ?

[postgres@by Chips-Demo]$ ping 192.168.1.1
PING 192.168.1.1 (192.168.1.1) 56(84) bytes of data.
64 bytes from 192.168.1.1: icmp_seq=4 ttl=255 time=0.627 ms
64 bytes from 192.168.1.1: icmp_seq=5 ttl=255 time=0.578 ms
64 bytes from 192.168.1.1: icmp_seq=6 ttl=255 time=0.548 ms
64 bytes from 192.168.1.1: icmp_seq=7 ttl=255 time=0.636 ms
64 bytes from 192.168.1.1: icmp_seq=8 ttl=255 time=0.674 ms
64 bytes from 192.168.1.1: icmp_seq=9 ttl=255 time=0.663 ms
^C
--- 192.168.1.1 ping statistics ---
9 packets transmitted, 6 received, 33% packet loss, time 7999ms
rtt min/avg/max/mdev = 0.548/0.621/0.674/0.044 ms

[liubenyuan]

And any suggestion in learning Chips2.0 ? I think a valuable tutorial is needed. And some documentary on the chips-demo design, may I help ?

I want to transfer large amount of data (4channel of WVGA streams via ethernet), and how could I use your design (as well as the chips2.0 language) to facilitate UDP data transmission ?

Best!

[dawsonjon]

Hi,

Glad you got it working. Main change was to invert the reset in source/nexys3.vhd.

There is some documentation for chips, although I would like to improve it, and would be most grateful for any contribution you would like to make. I will try to put together some more details about the implementation of the demo.

The chips demo may be a good starting point for a multi-channel UDP stream. TCP is significantly more complicated than UDP, so you would actually need to remove a fair bit of code. Take a look at source/server.h.

1. The lower level protocols could probably be left as they are.
2. put_tcp_packet() and get_tcp_packet() would need adapting to reflect the fields in a UDP packet.
3. server() would become a simple loop that continually passes data between the lower level protocols and the four application streams.
4. You would need to use the port fields to associate UDP packets with one of the four streams and route the data accordingly.

[anakena]

Hi, I try to take control of Atlys_tcp_socket for big data transfer in Windows 8 platform. I spend a lot of time to understand how to convert C files to V files (user_design.v and server.v) with no success. Currently, using directly atlys.py in scrip folder with some modifications (path files), I just happen to copy files in ATLYS folder. I use this command in a command prompt window : C:\Python27\python.exe C:\Atlys_tcp_socket\tcp_socket\trunk\scripts\atlys.py compile In C2verilog file in chip2 folder I read "compiles using Icarus verilog compiler" but I dont find any file with this name You say in readme.pdf file that some user have reported success using windows. Could you please help me, you understood I'm not very strong with linux platform Best regards

[dawsonjon]

Hi, Sorry for the delay replying. I haven't tried this in Windows myself, but I will try to help. If you have run atlys.py compile then you should find the .v files in the ATLYS folder. Please could you confirm if this is the case? Thanks Jon

[anakena]

Hi Jon, Don't worry for the delay, this give time to understand your code. That's it! I deal with your code now. I can make some modifications and it works. I have wrote a protocol step by step to build bit file using Windows (see the enclosure file). Very great job you have made. Your source files are very clear, the project is well structured ! Congratulations to seed your code !!! Now, it's up to me to make some modifications for my application. I plant to transfer large data file from a CCD scanner I built (240 Mpixels). At this time I use a PCI connection between PC ( in fact it's a Macintosh) and scanner. I will use UDP protocol and transfer data in real-time. I will cut each pixel line (12000 pixels) in 48 packets of 1500 byte. I have read the reply you made to Liubenyuan and I will manage with that. Thanks

Software setup** Install Xilinx ISE 13.4 (Spartan 6 is supported, last Webpack versions are locked on Zynq devices) Install Python27 (https://www.python.org/ftp/python/2.7.9/python-2.7.9.msi) Install Icarus Verilog (http://bleyer.org/icarus/iverilog-0.9.7_setup.exe) Add in Windows path = "C:\iverilog\bin;C:\Python27\;C:\Python27\Scripts;C:/Xilinx/13.4/ISE_DS/ISE/bin/nt64;" Move Atlys_tcp_socket folder to c:\ folder Install Chips2 inside Python folder with command "python C:/Atlys_tcp_socket/tcp_socket/trunk/chip2/setup.py Rename C:\Python27\Scripts\c2verilog to c2verilog.py

1) Delet files in project folder if modifications in source files**** cd c:/atlys_tcp_socket/tcp_socket/trunk/atlys/ rmdir /s /q c:\atlys_tcp_socket\tcp_socket\trunk\atlys\

2) Copy project files in ATLYS project folder***** cd.. python C:/Atlys_tcp_socket/tcp_socket/trunk/scripts/atlys.py

3) C to verilog convertion methode*** python C:/Python27/scripts/c2verilog.py C:/Atlys_tcp_socket/tcp_socket/trunk/source/user_design.c python C:/Python27/scripts/c2verilog.py C:/Atlys_tcp_socket/tcp_socket/trunk/source/server.c

4) Move verilog files to project folder***** move c:\atlys_tcp_socket\tcp_socket\trunk\user_design.v c:\atlys_tcp_socket\tcp_socket\trunk\atlys\ move c:\atlys_tcp_socket\tcp_socket\trunk\server.v c:\atlys_tcp_socket\tcp_socket\trunk\atlys\

5) Buid Xilinx FPGA files methode*** cd atlys xflow -synth xst_mixed.opt -p XC6Slx45-CSG324 -implement balanced.opt -config bitgen.opt ATLYS

Modifs to know if we dealing with atlys_tcp_socket**** 1) Change system frequency clock : In Atlys.vhd new CLK1=66.66 Mhz (CLKDV_DIVIDE => 1.5) old CLK1=50 Mhz (CLKDV_DIVIDE => 2.0)

2) Change HTML page : In user_design.c new "

Chips-2.0 THIERRY ATLYS Demo

\" old "

Chips-2.0 ATLYS Demo

\"

3) Change IP address 192.162.1.1 to 192.162.1.3 : In server.h new "const unsigned local_ip_address_lo = 0x0103u;" old "const unsigned local_ip_address_lo = 0x0101u;"

[liubenyuan]

Great ! I am busy with zynq these days and use AXI ethernet to transfer data. I will give nexys 4 a try !

It seem like we are both trying to send some video streams :)