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dawsonjon / Chips-Demo

Chips 2.0 Demo for Atlys Spartan 6 development platform. Web app using C to Verilog TCP/IP server.
MIT License
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build nexys3.py failed with 11 errors and 34 warnings #4

Closed liubenyuan closed 10 years ago

liubenyuan commented 10 years ago

Hi, I build with nexys3.py failed, below are the error messages.

I am sorry for those so many issue reports, may be i should try phimii first ...

Building Demo using Xilinx ise ....
Release 14.3 - Xflow P.40xd (lin64)
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.
xflow -synth xst_mixed.opt -p XC6Slx16-CSG324 -implement balanced.opt -config
bitgen.opt NEXYS3  

Using Flow File: /home/postgres/workspace/Chips-Demo/NEXYS3/fpga.flw 
Using Option File(s): 
 /home/postgres/workspace/Chips-Demo/NEXYS3/balanced.opt 
 /home/postgres/workspace/Chips-Demo/NEXYS3/bitgen.opt 
 /home/postgres/workspace/Chips-Demo/NEXYS3/xst_mixed.opt 

Creating Script File ... 

#----------------------------------------------#
# Starting program xst
# xst -ifn NEXYS3_xst.scr -ofn NEXYS3_xst.log -intstyle xflow 
#----------------------------------------------#
Reading design: /home/postgres/workspace/Chips-Demo/NEXYS3/NEXYS3.prj

=========================================================================
*                          HDL Parsing                                  *
=========================================================================
Analyzing Verilog file "/home/postgres/workspace/Chips-Demo/NEXYS3/user_design.v" into library work
Parsing module <user_design>.
Analyzing Verilog file "/home/postgres/workspace/Chips-Demo/NEXYS3/server.v" into library work
Parsing module <server>.
Parsing VHDL file "/home/postgres/workspace/Chips-Demo/source/serial_out.vhd" into library work
Parsing entity <serial_output>.
Parsing architecture <RTL> of entity <serial_output>.
Parsing VHDL file "/home/postgres/workspace/Chips-Demo/source/serial_in.vhd" into library work
Parsing entity <SERIAL_INPUT>.
Parsing architecture <RTL> of entity <serial_input>.
Parsing VHDL file "/home/postgres/workspace/Chips-Demo/source/ethernet.vhd" into library work
Parsing entity <ethernet>.
Parsing architecture <RTL> of entity <ethernet>.
Parsing VHDL file "/home/postgres/workspace/Chips-Demo/source/nexys3.vhd" into library work
Parsing entity <NEXYS3>.
Parsing architecture <RTL> of entity <nexys3>.

=========================================================================
*                            HDL Elaboration                            *
=========================================================================

Elaborating entity <NEXYS3> (architecture <RTL>) from library <work>.

Elaborating entity <ethernet> (architecture <RTL>) from library <work>.
Going to verilog side to elaborate module SERVER

Elaborating module <server>.
WARNING:HDLCompiler:413 - "/home/postgres/workspace/Chips-Demo/NEXYS3/server.v" Line 3626: Result of 13-bit expression is truncated to fit in 12-bit target.
WARNING:HDLCompiler:413 - "/home/postgres/workspace/Chips-Demo/NEXYS3/server.v" Line 3653: Result of 32-bit expression is truncated to fit in 12-bit target.
WARNING:HDLCompiler:413 - "/home/postgres/workspace/Chips-Demo/NEXYS3/server.v" Line 3680: Result of 32-bit expression is truncated to fit in 16-bit target.
WARNING:HDLCompiler:413 - "/home/postgres/workspace/Chips-Demo/NEXYS3/server.v" Line 3685: Result of 32-bit expression is truncated to fit in 12-bit target.
WARNING:HDLCompiler:413 - "/home/postgres/workspace/Chips-Demo/NEXYS3/server.v" Line 3697: Result of 32-bit expression is truncated to fit in 16-bit target.
WARNING:HDLCompiler:413 - "/home/postgres/workspace/Chips-Demo/NEXYS3/server.v" Line 3738: Result of 32-bit expression is truncated to fit in 12-bit target.
WARNING:HDLCompiler:413 - "/home/postgres/workspace/Chips-Demo/NEXYS3/server.v" Line 3753: Result of 32-bit expression is truncated to fit in 12-bit target.
WARNING:HDLCompiler:413 - "/home/postgres/workspace/Chips-Demo/NEXYS3/server.v" Line 3767: Result of 32-bit expression is truncated to fit in 16-bit target.
WARNING:HDLCompiler:413 - "/home/postgres/workspace/Chips-Demo/NEXYS3/server.v" Line 3791: Result of 32-bit expression is truncated to fit in 12-bit target.
WARNING:HDLCompiler:413 - "/home/postgres/workspace/Chips-Demo/NEXYS3/server.v" Line 3800: Result of 32-bit expression is truncated to fit in 16-bit target.
WARNING:HDLCompiler:413 - "/home/postgres/workspace/Chips-Demo/NEXYS3/server.v" Line 3801: Result of 32-bit expression is truncated to fit in 16-bit target.
"/home/postgres/workspace/Chips-Demo/NEXYS3/server.v" Line 3807. $display 0 (report at line: 107 in file: /media/storage/Projects/Chips-Demo/source/server.h)
WARNING:HDLCompiler:413 - "/home/postgres/workspace/Chips-Demo/NEXYS3/server.v" Line 3903: Result of 32-bit expression is truncated to fit in 16-bit target.
WARNING:HDLCompiler:413 - "/home/postgres/workspace/Chips-Demo/NEXYS3/server.v" Line 3952: Result of 32-bit expression is truncated to fit in 16-bit target.
WARNING:HDLCompiler:413 - "/home/postgres/workspace/Chips-Demo/NEXYS3/server.v" Line 3968: Result of 16-bit expression is truncated to fit in 1-bit target.
WARNING:HDLCompiler:413 - "/home/postgres/workspace/Chips-Demo/NEXYS3/server.v" Line 3969: Result of 16-bit expression is truncated to fit in 1-bit target.
WARNING:HDLCompiler:413 - "/home/postgres/workspace/Chips-Demo/NEXYS3/server.v" Line 3970: Result of 16-bit expression is truncated to fit in 1-bit target.
WARNING:HDLCompiler:413 - "/home/postgres/workspace/Chips-Demo/NEXYS3/server.v" Line 3972: Result of 16-bit expression is truncated to fit in 1-bit target.
Back to vhdl to continue elaboration
Going to verilog side to elaborate module USER_DESIGN

Elaborating module <user_design>.
WARNING:HDLCompiler:413 - "/home/postgres/workspace/Chips-Demo/NEXYS3/user_design.v" Line 3324: Result of 12-bit expression is truncated to fit in 11-bit target.
WARNING:HDLCompiler:413 - "/home/postgres/workspace/Chips-Demo/NEXYS3/user_design.v" Line 3351: Result of 32-bit expression is truncated to fit in 11-bit target.
WARNING:HDLCompiler:413 - "/home/postgres/workspace/Chips-Demo/NEXYS3/user_design.v" Line 3383: Result of 32-bit expression is truncated to fit in 11-bit target.
WARNING:HDLCompiler:413 - "/home/postgres/workspace/Chips-Demo/NEXYS3/user_design.v" Line 3406: Result of 32-bit expression is truncated to fit in 16-bit target.
WARNING:HDLCompiler:413 - "/home/postgres/workspace/Chips-Demo/NEXYS3/user_design.v" Line 3418: Result of 32-bit expression is truncated to fit in 11-bit target.
WARNING:HDLCompiler:413 - "/home/postgres/workspace/Chips-Demo/NEXYS3/user_design.v" Line 3433: Result of 32-bit expression is truncated to fit in 11-bit target.
WARNING:HDLCompiler:413 - "/home/postgres/workspace/Chips-Demo/NEXYS3/user_design.v" Line 3551: Result of 32-bit expression is truncated to fit in 16-bit target.
WARNING:HDLCompiler:413 - "/home/postgres/workspace/Chips-Demo/NEXYS3/user_design.v" Line 3552: Result of 32-bit expression is truncated to fit in 16-bit target.
WARNING:HDLCompiler:413 - "/home/postgres/workspace/Chips-Demo/NEXYS3/user_design.v" Line 3559: Result of 32-bit expression is truncated to fit in 11-bit target.
WARNING:HDLCompiler:413 - "/home/postgres/workspace/Chips-Demo/NEXYS3/user_design.v" Line 3684: Result of 32-bit expression is truncated to fit in 16-bit target.
WARNING:HDLCompiler:413 - "/home/postgres/workspace/Chips-Demo/NEXYS3/user_design.v" Line 3703: Result of 32-bit expression is truncated to fit in 1-bit target.
WARNING:HDLCompiler:413 - "/home/postgres/workspace/Chips-Demo/NEXYS3/user_design.v" Line 3704: Result of 32-bit expression is truncated to fit in 1-bit target.
WARNING:HDLCompiler:413 - "/home/postgres/workspace/Chips-Demo/NEXYS3/user_design.v" Line 3705: Result of 32-bit expression is truncated to fit in 1-bit target.
WARNING:HDLCompiler:413 - "/home/postgres/workspace/Chips-Demo/NEXYS3/user_design.v" Line 3706: Result of 32-bit expression is truncated to fit in 1-bit target.
WARNING:HDLCompiler:413 - "/home/postgres/workspace/Chips-Demo/NEXYS3/user_design.v" Line 3707: Result of 32-bit expression is truncated to fit in 1-bit target.
WARNING:HDLCompiler:413 - "/home/postgres/workspace/Chips-Demo/NEXYS3/user_design.v" Line 3709: Result of 32-bit expression is truncated to fit in 1-bit target.
WARNING:HDLCompiler:413 - "/home/postgres/workspace/Chips-Demo/NEXYS3/user_design.v" Line 3711: Result of 32-bit expression is truncated to fit in 1-bit target.
Back to vhdl to continue elaboration
ERROR:HDLCompiler:410 - "/home/postgres/workspace/Chips-Demo/source/nexys3.vhd" Line 173: Expression has 16 elements ; expected 32
ERROR:HDLCompiler:410 - "/home/postgres/workspace/Chips-Demo/source/nexys3.vhd" Line 177: Expression has 16 elements ; expected 32
ERROR:HDLCompiler:410 - "/home/postgres/workspace/Chips-Demo/source/nexys3.vhd" Line 181: Expression has 16 elements ; expected 32
ERROR:HDLCompiler:410 - "/home/postgres/workspace/Chips-Demo/source/nexys3.vhd" Line 186: Expression has 16 elements ; expected 32
ERROR:HDLCompiler:410 - "/home/postgres/workspace/Chips-Demo/source/nexys3.vhd" Line 191: Expression has 16 elements ; expected 32
ERROR:HDLCompiler:410 - "/home/postgres/workspace/Chips-Demo/source/nexys3.vhd" Line 196: Expression has 16 elements ; expected 32
ERROR:HDLCompiler:410 - "/home/postgres/workspace/Chips-Demo/source/nexys3.vhd" Line 201: Expression has 16 elements ; expected 32
ERROR:HDLCompiler:432 - "/home/postgres/workspace/Chips-Demo/NEXYS3/user_design.v" Line 127: Formal <input_switches> has no actual or default value.
ERROR:HDLCompiler:432 - "/home/postgres/workspace/Chips-Demo/NEXYS3/user_design.v" Line 128: Formal <input_buttons> has no actual or default value.
ERROR:HDLCompiler:432 - "/home/postgres/workspace/Chips-Demo/NEXYS3/user_design.v" Line 129: Formal <input_socket> has no actual or default value.
ERROR:HDLCompiler:432 - "/home/postgres/workspace/Chips-Demo/NEXYS3/user_design.v" Line 130: Formal <input_rs232_rx> has no actual or default value.
Netlist NEXYS3(RTL) remains a blackbox, due to errors in its contents
--> 

Total memory usage is 353228 kilobytes

Number of errors   :   11 (   0 filtered)
Number of warnings :   34 (   0 filtered)
Number of infos    :    0 (   0 filtered)

ERROR:Xflow - Program xst returned error code 6. Aborting flow execution...
dawsonjon commented 10 years ago

I think the problem might be that you are using the latest version of chips, but Chips-Demo was developed using an older version.

Since I am actively developing Chips, I am making changes fairly frequently. To work around this, I have included the correct version of Chips within the Chips-Demo. This is managed using the git submodule feature. Performing a git submodule init, followed by a git submodule sync should give you a local copy of the correct chips version. My intention is to update Chips-Demo to use the newest version of Chips from time to time.

I think there may have been an error in the .gitmodules URL, but I have corrected this. Please could you confirm whether:

  1. The git submodule process is now working.
  2. Whether the build errors still occur using the local chips2 submodule?
liubenyuan commented 10 years ago

Hi, nexys3.py works with local chips2.0 version. I am sorry for the repost of the same issue.

I am now moving to understand your demo code and migrating to UDP.

Best.

liubenyuan commented 10 years ago

Hi, one suggestion, may we we should remove the ATLYS/ and NEXYS3/ folders, as the contents in these folders are mid-stage outputs of xst, map, and xflow.