jpt13653903
commented
2 years ago You have to have it when you simulate. It's not useful in synthesis.
You can use a finer timescale when you're simulating ASICs (remember that Verilog et. al. is meant for ASIC, the FPGA world just happen to use it). When you're simulating ASIC designs, you sometimes want to have gate-level timing accurate models, in which case you use a finer timescale.
With FPGAs, the compiler's timing analyser takes care of this step for you. A behavioural simulation is generally sufficient.
Hi @jpt13653903 How often do you change/use this? I know it sets the #delay precision, but what motivates finer timescales other than this?