issue while running arty.py

bhatmahadev6 commented 3 years ago

Traceback (most recent call last): File "arty.py", line 156, in main() File "arty.py", line 149, in main builder.build(**builder_kwargs, run=args.build) File "/home/litex/litex/soc/integration/builder.py", line 255, in build self._generate_csr_map() File "/home/litex/litex/soc/integration/builder.py", line 208, in _generate_csr_map write_to_file(os.path.realpath(self.csr_csv), csr_csv_contents) File "/home/litex/litex/build/tools.py", line 40, in write_to_file with open(filename, "w", newline=newline) as f: FileNotFoundError: [Errno 2] No such file or directory: '/home/iisclap/Documents/litex_experiments_1/litex-experiments/litex/litex-boards/litex_boards/targets/build/arty/csr.csv'

dayjaby commented 3 years ago

Hey! All commands are expected to be run from the root directory of the repository. Can you try to run the following line from there?

export LITEX_BOARD=arty
./litex/litex-boards/litex_boards/targets/$LITEX_BOARD.py \
  --toolchain vivado \
  --cpu-type vexriscv \
  --cpu-variant imac+debug \
  --with-etherbone \
  --csr-csv build/$LITEX_BOARD/csr.csv \
  --timer-uptime \
  --with-sdcard \
  --build

For me it resulted in the following csr file being generated:

~/Development/litex-experiments$ find . | grep csr.csv
./build/arty/csr.csv

bhatmahadev6 commented 3 years ago

okay but can you please share your zip which is having build over mail ?

I can diff check if there are any differences.Please !

bhatmahadev6 commented 3 years ago

i meant the zip of entire litex-experiments which is locally cloned and its successfully running one.

bhatmahadev6 commented 3 years ago

I tried running inside litex_experiments i guess this is the root directory.

iisclap@iisclap-Inspiron-5537:~/litex-experiments$ export LITEX_BOARD=arty iisclap@iisclap-Inspiron-5537:~/litex-experiments$ ./litex/litex-boards/litex_boards/targets/$LITEX_BOARD.py \

--toolchain vivado \ --cpu-type vexriscv \ --cpu-variant imac+debug \ --with-etherbone \ --csr-csv build/$LITEX_BOARD/csr.csv \ --timer-uptime \ --with-sdcard \ --build Compat: SoCSDRAM is deprecated since 2020-03-24 and will soon no longer work, please update. Switch to SoCCore/add_sdram/soc_core_args instead...........thanks :) INFO:SoC: _ _
INFO:SoC: / / () /____ | |//
INFO:SoC: / // / / -)> <
INFO:SoC: /____//_/_//||
INFO:SoC: Build your hardware, easily! INFO:SoC:-------------------------------------------------------------------------------- INFO:SoC:Creating SoC... (2021-05-31 13:46:34) INFO:SoC:-------------------------------------------------------------------------------- INFO:SoC:FPGA device : xc7a35ticsg324-1L. INFO:SoC:System clock: 100.00MHz. INFO:SoCBusHandler:Creating Bus Handler... INFO:SoCBusHandler:32-bit wishbone Bus, 4.0GiB Address Space. INFO:SoCBusHandler:Adding reserved Bus Regions... INFO:SoCBusHandler:Bus Handler created. INFO:SoCCSRHandler:Creating CSR Handler... INFO:SoCCSRHandler:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations). INFO:SoCCSRHandler:Adding reserved CSRs... INFO:SoCCSRHandler:CSR Handler created. INFO:SoCIRQHandler:Creating IRQ Handler... INFO:SoCIRQHandler:IRQ Handler (up to 32 Locations). INFO:SoCIRQHandler:Adding reserved IRQs... INFO:SoCIRQHandler:IRQ Handler created. INFO:SoC:-------------------------------------------------------------------------------- INFO:SoC:Initial SoC: INFO:SoC:-------------------------------------------------------------------------------- INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space. INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations). INFO:SoC:IRQ Handler (up to 32 Locations). INFO:SoC:-------------------------------------------------------------------------------- INFO:SoCBusHandler:io0 Region added at Origin: 0x80000000, Size: 0x80000000, Mode: RW, Cached: False Linker: False. INFO:SoCBusHandler:cpu_bus0 added as Bus Master. INFO:SoCBusHandler:cpu_bus1 added as Bus Master. INFO:SoCBusHandler:vexriscv_debug Region added at Origin: 0xf00f0000, Size: 0x00000100, Mode: RW, Cached: False Linker: False. INFO:SoCBusHandler:vexriscv_debug added as Bus Slave. INFO:SoCBusHandler:rom Region added at Origin: 0x00000000, Size: 0x00010000, Mode: R, Cached: True Linker: False. INFO:SoCBusHandler:rom added as Bus Slave. INFO:SoC:RAM rom added Origin: 0x00000000, Size: 0x00010000, Mode: R, Cached: True Linker: False. INFO:SoCBusHandler:sram Region added at Origin: 0x10000000, Size: 0x00002000, Mode: RW, Cached: True Linker: False. INFO:SoCBusHandler:sram added as Bus Slave. INFO:SoC:RAM sram added Origin: 0x10000000, Size: 0x00002000, Mode: RW, Cached: True Linker: False. INFO:SoCIRQHandler:uart IRQ allocated at Location 0. INFO:SoCIRQHandler:timer0 IRQ allocated at Location 1. INFO:S7PLL:Creating S7PLL, speedgrade -1. INFO:S7PLL:Registering Single Ended ClkIn of 100.00MHz. INFO:S7PLL:Creating ClkOut0 sys of 100.00MHz (+-10000.00ppm). INFO:S7PLL:Creating ClkOut1 sys4x of 400.00MHz (+-10000.00ppm). INFO:S7PLL:Creating ClkOut2 sys4x_dqs of 400.00MHz (+-10000.00ppm). INFO:S7PLL:Creating ClkOut3 idelay of 200.00MHz (+-10000.00ppm). INFO:S7PLL:Creating ClkOut4 eth of 25.00MHz (+-10000.00ppm). INFO:SoCCSRHandler:ddrphy CSR allocated at Location 0. INFO:SoCBusHandler:main_ram Region added at Origin: 0x40000000, Size: 0x10000000, Mode: RW, Cached: True Linker: False. INFO:SoCBusHandler:main_ram added as Bus Slave. INFO:SoCCSRHandler:ethphy CSR allocated at Location 1. INFO:SoCBusHandler:master2 added as Bus Master. INFO:SoCCSRHandler:leds CSR allocated at Location 2. INFO:SoCBusHandler:sdblock2mem added as Bus Master. INFO:SoCBusHandler:sdmem2block added as Bus Master. INFO:S7PLL:Config: divclk_divide : 1 clkout0_freq : 100.00MHz clkout0_divide: 16 clkout0_phase : 0.00° clkout1_freq : 400.00MHz clkout1_divide: 4 clkout1_phase : 0.00° clkout2_freq : 400.00MHz clkout2_divide: 4 clkout2_phase : 90.00° clkout3_freq : 200.00MHz clkout3_divide: 8 clkout3_phase : 0.00° clkout4_freq : 25.00MHz clkout4_divide: 64 clkout4_phase : 0.00° vco : 1600.00MHz clkfbout_mult : 16 INFO:SoCBusHandler:csr Region added at Origin: 0xf0000000, Size: 0x00010000, Mode: RW, Cached: False Linker: False. INFO:SoCBusHandler:csr added as Bus Slave. INFO:SoCCSRHandler:bridge added as CSR Master. INFO:SoCBusHandler:Interconnect: InterconnectShared (5 <-> 5). INFO:SoCCSRHandler:ctrl CSR allocated at Location 3. INFO:SoCCSRHandler:identifier_mem CSR allocated at Location 4. INFO:SoCCSRHandler:sdblock2mem CSR allocated at Location 5. INFO:SoCCSRHandler:sdcore CSR allocated at Location 6. INFO:SoCCSRHandler:sdirq CSR allocated at Location 7. INFO:SoCCSRHandler:sdmem2block CSR allocated at Location 8. INFO:SoCCSRHandler:sdphy CSR allocated at Location 9. INFO:SoCCSRHandler:sdram CSR allocated at Location 10. INFO:SoCCSRHandler:timer0 CSR allocated at Location 11. INFO:SoCCSRHandler:uart CSR allocated at Location 12. INFO:SoC:-------------------------------------------------------------------------------- INFO:SoC:Finalized SoC: INFO:SoC:-------------------------------------------------------------------------------- INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space. IO Regions: (1) io0 : Origin: 0x80000000, Size: 0x80000000, Mode: RW, Cached: False Linker: False Bus Regions: (5) rom : Origin: 0x00000000, Size: 0x00010000, Mode: R, Cached: True Linker: False sram : Origin: 0x10000000, Size: 0x00002000, Mode: RW, Cached: True Linker: False main_ram : Origin: 0x40000000, Size: 0x10000000, Mode: RW, Cached: True Linker: False csr : Origin: 0xf0000000, Size: 0x00010000, Mode: RW, Cached: False Linker: False vexriscv_debug : Origin: 0xf00f0000, Size: 0x00000100, Mode: RW, Cached: False Linker: False Bus Masters: (5)

cpu_bus0

cpu_bus1

master2

sdblock2mem

sdmem2block Bus Slaves: (5)

vexriscv_debug

rom

sram

main_ram

csr INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations). CSR Locations: (13)

ddrphy : 0

ethphy : 1

leds : 2

ctrl : 3

identifier_mem : 4

sdblock2mem : 5

sdcore : 6

sdirq : 7

sdmem2block : 8

sdphy : 9

sdram : 10

timer0 : 11

uart : 12 INFO:SoC:IRQ Handler (up to 32 Locations). IRQ Locations: (2)

uart : 0

timer0 : 1 INFO:SoC:-------------------------------------------------------------------------------- Traceback (most recent call last): File "./litex/litex-boards/litex_boards/targets/arty.py", line 156, in main() File "./litex/litex-boards/litex_boards/targets/arty.py", line 149, in main builder.build(**builder_kwargs, run=args.build) File "/home/litex/litex/soc/integration/builder.py", line 255, in build self._generate_csr_map() File "/home/litex/litex/soc/integration/builder.py", line 208, in _generate_csr_map write_to_file(os.path.realpath(self.csr_csv), csr_csv_contents) File "/home/litex/litex/build/tools.py", line 40, in write_to_file with open(filename, "w", newline=newline) as f: FileNotFoundError: [Errno 2] No such file or directory: '/home/iisclap/litex-experiments/build/arty/csr.csv' iisclap@iisclap-Inspiron-5537:~/litex-experiments$

dayjaby commented 3 years ago

Ok, uploading it right now. The csr.csv is an output file; so the only reason why it cannot write to it is if the build/arty directories are not created. Can you create them manually? Can you check with ls -al that you have all the necessary permissions to write into it?

bhatmahadev6 commented 3 years ago

Okay.

On Mon, 31 May, 2021, 2:25 pm David Jablonski, @.***> wrote:

Ok, uploading it right now. The csr.csv is an output file; so the only reason why it cannot write to it is if the build/arty directories are not created. Can you create them manually? Can you check with ls -al that you have all the necessary permissions to write into it?

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dayjaby commented 3 years ago

After that, feel free to test it in here: https://drive.google.com/file/d/1PY4X-OCv869Rl4oyT3ZrFXPy3_tXdIlT/view?usp=sharing

The last reason that I can think of is that some LiteX versions are not the same / not up-to-date. I added instructions to the front README.md how to install the exact same versions of LiteX within a virtual environment.

bhatmahadev6 commented 3 years ago

Thanks, I'll check it out.

On Mon, 31 May, 2021, 2:28 pm David Jablonski, @.***> wrote:

After that, feel free to test it in here: https://drive.google.com/file/d/1PY4X-OCv869Rl4oyT3ZrFXPy3_tXdIlT/view?usp=sharing

The last reason that I can think of is that some LiteX versions are not the same / not up-to-date. I added instructions to the front README.md how to install the exact same versions of LiteX within a virtual environment.

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dayjaby commented 3 years ago

Please use the same link again. This time the NuttX firmware is included. I got NuttX running with the following commands:

sudo apt install python3-virtualenv
virtualenv litex-env
source litex-env/bin/activate
cd litex
python3 litex_setup.py submodules
python3 litex_setup.py install
cd ..
./litex/litex-boards/litex_boards/targets/$LITEX_BOARD.py   --toolchain vivado   --cpu-type vexriscv   --cpu-variant imac+debug   --with-etherbone   --csr-csv build/$LITEX_BOARD/csr.csv   --timer-uptime   --with-sdcard   --generated-dir os/nuttx/nuttx/arch/risc-v/src/litex/hardware/generated   --jinja-templates templates   --filter-templates csr_defines.h csr.h soc.h   --load

and then (the USB port might be different for you!):

make nuttx
litex_term --serial-boot --kernel os/nuttx/nuttx/nuttx.bin /dev/ttyUSB1

results in

Switching SDRAM to hardware control.
Memtest at 0x40000000 (2MiB)...
  Write: 0x40000000-0x40200000 2MiB     
   Read: 0x40000000-0x40200000 2MiB     
Memtest OK
Memspeed at 0x40000000 (2MiB)...
  Write speed: 25MiB/s
   Read speed: 19MiB/s

--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
[LXTERM] Received firmware download request from the device.
[LXTERM] Uploading nuttx.bin to 0x40000000 (85244 bytes)...
[LXTERM] Upload complete (9.9KB/s).
[LXTERM] Booting the device.
[LXTERM] Done.
Executing booted program at 0x40000000

--============= Liftoff! ===============--

NuttShell (NSH) NuttX-10.0.1
nsh> help
help usage:  help [-v] [<cmd>]

  ?       echo    help    ls      mh      mv      ps      uname   
  cat     free    kill    mb      mount   mw      sleep   usleep  

Builtin Apps:
  getprime  sh        hello     nsh

bhatmahadev6 commented 3 years ago

Thank you its running fine now. There are few apps like hello and get prime .how can we add more examples. Like those ??

Thanks Mahadev

On Tue, 1 Jun, 2021, 1:17 pm David Jablonski, @.***> wrote:

Please use the same link again. This time the NuttX firmware is included. I got NuttX running with the following commands:

sudo apt install python3-virtualenv virtualenv litex-env source litex-env/bin/activate cd litex python3 litex_setup.py submodules python3 litex_setup.py install cd .. ./litex/litex-boards/litex_boards/targets/$LITEX_BOARD.py --toolchain vivado --cpu-type vexriscv --cpu-variant imac+debug --with-etherbone --csr-csv build/$LITEX_BOARD/csr.csv --timer-uptime --with-sdcard --generated-dir os/nuttx/nuttx/arch/risc-v/src/litex/hardware/generated --jinja-templates templates --filter-templates csr_defines.h csr.h soc.h --load

and then (the USB port might be different for you!):

make nuttx litex_term --serial-boot --kernel os/nuttx/nuttx/nuttx.bin /dev/ttyUSB1

results in

Switching SDRAM to hardware control. Memtest at 0x40000000 (2MiB)... Write: 0x40000000-0x40200000 2MiB Read: 0x40000000-0x40200000 2MiB Memtest OK Memspeed at 0x40000000 (2MiB)... Write speed: 25MiB/s Read speed: 19MiB/s

--============== Boot ==================-- Booting from serial... Press Q or ESC to abort boot completely. sL5DdSMmkekro [LXTERM] Received firmware download request from the device. [LXTERM] Uploading nuttx.bin to 0x40000000 (85244 bytes)... [LXTERM] Upload complete (9.9KB/s). [LXTERM] Booting the device. [LXTERM] Done. Executing booted program at 0x40000000

--============= Liftoff! ===============--

NuttShell (NSH) NuttX-10.0.1 nsh> help help usage: help [-v] []

? echo help ls mh mv ps uname cat free kill mb mount mw sleep usleep

Builtin Apps: getprime sh hello nsh

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dayjaby commented 3 years ago

Go to os/nuttx/nuttx and run make menuconfig. Go to applications (the bottom most afaik) and add some other examples.

bhatmahadev6 commented 3 years ago

Also just for info, why they have used the renode to run on the docker,doesn't it serve the same purpose of running locally.

have you ran the renode on the docker anytime ?

Mahadev

On Tue, 1 Jun, 2021, 1:39 pm David Jablonski, @.***> wrote:

Go to os/nuttx/nuttx and run make menuconfig. Go to applications (the bottom most afaik) and add some other examples.

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dayjaby commented 3 years ago

Docker is useful if you do not want to pollute your development environment. But in this case I didn't try it. Closing this for now, but if you have more questions, feel free to ask :)

bhatmahadev6 commented 3 years ago

Thanks for info.will revert if I need any help.

On Tue, 1 Jun, 2021, 3:32 pm David Jablonski, @.***> wrote:

Closed #1 https://github.com/dayjaby/litex-experiments/issues/1.

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dayjaby / litex-experiments

issue while running arty.py #1