D1s - AssertionError

[kassane]

Hi @daym

Manual D1s

Trying to extract D1s occurs this error:

WARNING:root:'HS_TMR1_CURNT_HI_REG': Invalid field ['HS_TMR1_CUR_VALUE_LO should be done before HS_TMR1_CUR_VALUE_HI.', '', '', '']: Bitrange error
WARNING:root:'HS_TMR1_INTV_HI_REG': Invalid field ['HSTimer1 is a 56-bit counter. The interval value consists of two parts: HS_TMR1_INTV_VALUE_LO acts as', '', '', '']: Bitrange error
WARNING:root:Field could not be parsed as a bitrange: ['the  bit[31', '0]  and  HS_TMR1_INTV_VALUE_HI  acts  as  the  bit[55', '32].  To  read  or  write  the  interval  value,']
WARNING:root:'HS_TMR1_INTV_HI_REG': Invalid field ['HS_TMR1_INTV_LO_REG should be done before HS_TMR1_INTV_HI_REG.', '', '', '']: Bitrange error
WARNING:root:Could not interpret enumeratedValue '0': 'High-level trigger' in field 'IRQ_MD0' in register 'IRQ_MODE0_REG' (num_bits = 32)
WARNING:root:Could not interpret enumeratedValue '1': 'Rising edge trigger' in field 'IRQ_MD0' in register 'IRQ_MODE0_REG' (num_bits = 32)
WARNING:root:Could not interpret enumeratedValue '0': 'High-level trigger' in field 'IRQ_MD1' in register 'IRQ_MODE1_REG' (num_bits = 32)
WARNING:root:Could not interpret enumeratedValue '1': 'Rising edge trigger' in field 'IRQ_MD1' in register 'IRQ_MODE1_REG' (num_bits = 32)
WARNING:root:Could not interpret enumeratedValue '0': 'High-level trigger' in field 'IRQ_MD2' in register 'IRQ_MODE2_REG' (num_bits = 32)
WARNING:root:Could not interpret enumeratedValue '1': 'Rising edge trigger' in field 'IRQ_MD2' in register 'IRQ_MODE2_REG' (num_bits = 32)
WARNING:root:Could not interpret enumeratedValue '0': 'High-level trigger' in field 'IRQ_MD3' in register 'IRQ_MODE3_REG' (num_bits = 32)
WARNING:root:Could not interpret enumeratedValue '1': 'Rising edge trigger' in field 'IRQ_MD3' in register 'IRQ_MODE3_REG' (num_bits = 32)
WARNING:root:Could not interpret enumeratedValue '0': 'High-level trigger' in field 'IRQ_MD4' in register 'IRQ_MODE4_REG' (num_bits = 32)
WARNING:root:Could not interpret enumeratedValue '1': 'Rising edge trigger' in field 'IRQ_MD4' in register 'IRQ_MODE4_REG' (num_bits = 32)
INFO:root:'LEDC': Register block: None: {'LEDC_CTRL_REG': [0], 'LEDC_DATA_FINISH_CNT_REG': [8], 'LEDC_DATA_REG': [20], 'LEDC_DMA_CTRL_REG': [24], 'LEDC_INTERRUPT_CTRL_REG': [28], 'LEDC_INT_STS_REG': [32], 'LEDC_WAIT_TIME0_CTRL_REG': [16], 'LEDC_WAIT_TIME1_CTRL_REG': [40], 'LED_RESET_TIMING_CTRL_REG': [12], 'LED_T01_TIMING_CTRL_REG': [4]}
INFO:root:'LEDC': Register block: ('N', (0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31)): {'LEDC_FIFO_DATA_X': [48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92, 96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 148, 152, 156, 160, 164, 168, 172]}
WARNING:root:'OWA_RX_CHSTA1': Field names are not all known; for example the one described by: '00: Copying is permitted without restriction \n01: One generation of copies may be made \n10: Condition is not be used \n11: No copying is permitted '
WARNING:root:'OWA_TX_CHSTA1': Field names are not all known; for example the one described by: '00: Copying is permitted without restriction \n01: One generation of copies may be made \n10: Condition not be used \n11: No copying is permitted '
WARNING:root:register 'OWA_RX_CHSTA0' field 'EMP' enum variants are not unique ([['000', ' 2 Audio channels without pre-emphasis '], ['001', ' 2 Audio channels with 50 μs/15 μs pre-emphasis '], ['010', ' Reserved (For 2 Audio channels with pre-emphasis) '], ['011', ' Reserved (For 2 Audio channels with pre-emphasis)  100 to 111: Reserved  For bit 1 = ‘1’, Other than Linear PCM applications: '], ['000', ' Default state  001 to 111: Reserved ']], counter = 6). Giving up.
WARNING:root:register 'OWA_RX_CHSTA1' field 'WL' enum variants are not unique ([['000', ' Not indicated '], ['001', ' 16 bits '], ['010', ' 18 bits '], ['100', ' 19 bits '], ['101', ' 20 bits '], ['110', ' 17 bits '], ['111', ' Reserved  For bit 0 = ‘1’: '], ['000', ' Not indicated '], ['001', ' 20 bits '], ['010', ' 22 bits '], ['100', ' 23 bits '], ['101', ' 24 bits '], ['110', ' 21 bits '], ['111', ' Reserved ']], counter = 3). Giving up.
WARNING:root:register 'OWA_TX_CHSTA0' field 'EMP' enum variants are not unique ([['000', ' 2 audio channels without pre-emphasis '], ['001', ' 2 audio channels with 50 μs/15 μs pre-emphasis '], ['010', ' Reserved (for 2 audio channels with pre-emphasis) '], ['011', ' Reserved (for 2 audio channels with pre-emphasis)  100 to 111: Reserved  For bit 1 = “1”, other than Linear PCM applications: '], ['000', ' Default state  001 to 111: Reserved ']], counter = 6). Giving up.
WARNING:root:register 'OWA_TX_CHSTA1' field 'WL' enum variants are not unique ([['000', ' Not indicated '], ['001', ' 16 bits '], ['010', ' 18 bits '], ['100', ' 19 bits '], ['101', ' 20 bits '], ['110', ' 17 bits '], ['111', ' Reserved  For bit 0 = “1”: '], ['000', ' Not indicated '], ['001', ' 20 bits '], ['010', ' 22 bits '], ['100', ' 23 bits '], ['101', ' 24 bits '], ['110', ' 21 bits '], ['111', ' Reserved ']], counter = 3). Giving up.
INFO:root:'RISC PLIC': Register block: None: {'PLIC_CTRL_REG': [2097148], 'PLIC_MCLAIM_REG': [2097156], 'PLIC_MTH_REG': [2097152], 'PLIC_SCLAIM_REG': [2101252], 'PLIC_STH_REG': [2101248]}
INFO:root:'RISC PLIC': Register block: ('n', (0, 1, 2, 3, 4, 5, 6, 7, 8)): {'PLIC_IP_REGn': [4096, 4100, 4104, 4108, 4112, 4116, 4120, 4124, 4128], 'PLIC_MIE_REGn': [8192, 8196, 8200, 8204, 8208, 8212, 8216, 8220, 8224], 'PLIC_SIE_REGn': [8320, 8324, 8328, 8332, 8336, 8340, 8344, 8348, 8352]}
INFO:root:'RISC PLIC': Register block: ('n', (1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212, 213, 214, 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228, 229, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, 241, 242, 243, 244, 245, 246, 247, 248, 249, 250, 251, 252, 253, 254, 255)): {'PLIC_PRIO_REGn': [4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92, 96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 148, 152, 156, 160, 164, 168, 172, 176, 180, 184, 188, 192, 196, 200, 204, 208, 212, 216, 220, 224, 228, 232, 236, 240, 244, 248, 252, 256, 260, 264, 268, 272, 276, 280, 284, 288, 292, 296, 300, 304, 308, 312, 316, 320, 324, 328, 332, 336, 340, 344, 348, 352, 356, 360, 364, 368, 372, 376, 380, 384, 388, 392, 396, 400, 404, 408, 412, 416, 420, 424, 428, 432, 436, 440, 444, 448, 452, 456, 460, 464, 468, 472, 476, 480, 484, 488, 492, 496, 500, 504, 508, 512, 516, 520, 524, 528, 532, 536, 540, 544, 548, 552, 556, 560, 564, 568, 572, 576, 580, 584, 588, 592, 596, 600, 604, 608, 612, 616, 620, 624, 628, 632, 636, 640, 644, 648, 652, 656, 660, 664, 668, 672, 676, 680, 684, 688, 692, 696, 700, 704, 708, 712, 716, 720, 724, 728, 732, 736, 740, 744, 748, 752, 756, 760, 764, 768, 772, 776, 780, 784, 788, 792, 796, 800, 804, 808, 812, 816, 820, 824, 828, 832, 836, 840, 844, 848, 852, 856, 860, 864, 868, 872, 876, 880, 884, 888, 892, 896, 900, 904, 908, 912, 916, 920, 924, 928, 932, 936, 940, 944, 948, 952, 956, 960, 964, 968, 972, 976, 980, 984, 988, 992, 996, 1000, 1004, 1008, 1012, 1016, 1020]}
WARNING:root:register 'TP_CTRL0' field 'FS_DIV' enum variants are not unique ([['0000', ' CLK_IN/2  '], ['0001', ' CLK_IN/2  '], ['0010', ' CLK_IN/2   ….   '], ['1111', ' CLK_IN/2  ']], counter = 2). Giving up.
Traceback (most recent call last):
  File "/home/kassane/Documents/allwinner-register-interface-extractor/phase3.py", line 1086, in <module>
    summary, container = parse_Summary(container, module)
  File "/home/kassane/Documents/allwinner-register-interface-extractor/phase3.py", line 1014, in parse_Summary
    assert len(row) == 3, (row, module.rows)
AssertionError: (['TVD0 '], [['TVD_TOP ', '0x05C00000 '], ['TVD0 ', '0x05C01000   ']])
make: *** [Makefile:16: phase3_host.svd] Error 1

[daym]

On page 529, the section headers TVD_TOP and TVD0 are not bold or in any way otherwise marked. Therefore, they are not recognized as section headers (those would be with an element # in front in phase2_result.py). But they don't have an offset either, so they are not registers. So what are they?

Anyway, worked around that in main branch, commit 96b2685102267f58390916e64f921b9cce8cd203 (to make them be classified as section headers).

Please test.

Furthermore, made Makefile detect a cpu named just "RISC" as "riscv" in main branch, commit 1bbca1b0abff5d998f829ca452f3c6823242a4c9.

[kassane]

Well done.

[kassane]

cc: @daym

Manual v1.2

pdftohtml -nodrm -xml D1-H_1-2.pdf partsvol1/a >/dev/null
Document has copy-protection bit set.
# Invalid multibyte character
sed -i -e 's;\xcb\xce\xcc\xe5;;' -e 's;\xce\xa2\xc8\xed\xd1\xc5\xba\xda;;' partsvol1/a.xml
./extract.py partsvol1/a.xml D1-H_1-2.pdf > "phase2_result.py".new && mv "phase2_result.py".new "phase2_result.py"
WARNING:root:ignored h4 of 'TVE_TOP ' in table 'Module List' since it's most likely a typo
WARNING:root:ignored h4 of 'TVD_TOP ' in table 'Module List' since it's most likely a typo
Traceback (most recent call last):
  File "/home/kassane/allwinner-register-interface-extractor/./extract.py", line 457, in <module>
    traverse(state, root)
  File "/home/kassane/allwinner-register-interface-extractor/./extract.py", line 450, in traverse
    traverse(state, node, indent + 1, fontspecs)
  File "/home/kassane/allwinner-register-interface-extractor/./extract.py", line 446, in traverse
    state.process_text(text, attrib, xx)
  File "/home/kassane/allwinner-register-interface-extractor/./extract.py", line 178, in process_text
    assert (attrib["meaning"] == "h4" and xx == {"b"}) or attrib["meaning"] == "table-cell" or attrib["meaning"] == "h3", (self.page_number, attrib, xx)
AssertionError: ('559', {'left': '481', 'font': "(('color', '#000000'), ('family', 'ABCDEE+Calibri'), ('size', '16'))", 'meaning': ''}, set())
make: *** [Makefile:13: phase2_result.py] Error 1

v1.2.tar.gz

[daym]

I tried both the files from v1.2.tar.gz and they work for me with current master.