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# Invalid multibyte character
sed -i -e 's;\xcb\xce\xcc\xe5;;' -e 's;\xce\xa2\xc8\xed\xd1\xc5\xba\xda;;' partsvol1/a.xml
./extract.py partsvol1/a.xml D1.pdf > "phase2_result.py".new && mv "phase2_result.py".new "phase2_result.py"
WARNING:root:ignored h4 of 'TVE_TOP ' in table 'Module List' since it's most likely a typo
WARNING:root:ignored h4 of 'TVD_TOP ' in table 'Module List' since it's most likely a typo
WARNING:root:ignored h4 of 'EHCI Capability Register' in table 'Module List' since it's most likely a typo
python3 phase3.py phase2_result.py >phase3_host.svd.new && mv phase3_host.svd.new phase3_host.svd
WARNING:root:Table formatting in PDF is unknown: header=([], ['Register_Name', 'Offset', 'Description']), row=['VRA1SPEEDUP_DOWN_CTRL  0x0054 ', 'VRA1 Speedup Down Control Register ']
WARNING:root:Table formatting in PDF is unknown: header=([], ['Register_Name', 'Offset', 'Description']), row=['Analog Domain Register ']
WARNING:root:Table formatting in PDF is unknown: header=([], ['Register_Name', 'Offset', 'Description']), row=['EHCI Capability Register']
WARNING:root:Table formatting in PDF is unknown: header=([], ['Register_Name', 'Offset', 'Register_Description']), row=['CSIC TOP register list: ']
WARNING:root:Table formatting in PDF is unknown: header=([], ['Register_Name', 'Offset', 'Register_Description']), row=['PARSER0 register list: ']
WARNING:root:Table formatting in PDF is unknown: header=([], ['Register_Name', 'Offset', 'Register_Description']), row=['CSIC_PRS_NCSIC_BT656_HEAD_CFG_']
WARNING:root:Table formatting in PDF is unknown: header=([], ['Register_Name', 'Offset', 'Register_Description']), row=['CSIC_PRS_NCSIC_RX_SIGNAL0_DLY_']
WARNING:root:Table formatting in PDF is unknown: header=([], ['Register_Name', 'Offset', 'Register_Description']), row=['CSIC_PRS_NCSIC_RX_SIGNAL5_DLY_']
WARNING:root:Table formatting in PDF is unknown: header=([], ['Register_Name', 'Offset', 'Register_Description']), row=['CSIC_PRS_NCSIC_RX_SIGNAL6_DLY_']
WARNING:root:Table formatting in PDF is unknown: header=([], ['Register_Name', 'Offset', 'Register_Description']), row=['DMA0/1 register list: ']
WARNING:root:Table formatting in PDF is unknown: header=([], ['Register_Name', 'Offset', 'Register_Description']), row=['CSIC_DMA_BUF_ADDR_FIFO0_ENTR']
WARNING:root:Table formatting in PDF is unknown: header=([], ['Register_Name', 'Offset', 'Register_Description']), row=['CSIC_DMA_BUF_ADDR_FIFO1_ENTR']
WARNING:root:Table formatting in PDF is unknown: header=([], ['Register_Name', 'Offset', 'Register_Description']), row=['CSIC_DMA_BUF_ADDR_FIFO2_ENTR']
WARNING:root:Table formatting in PDF is unknown: header=([], ['Register_Name', 'Offset', 'Register_Description']), row=['CSIC_DMA_BUF_ADDR_FIFO_CON_R']
WARNING:root:Table formatting in PDF is unknown: header=(['Offset: 0x002C'], ['Bit', 'Read/Write', 'Default/Hex', 'Description']), row=['Before performing the burning operation, ensure that the power supply of the eFuse power pin is stable.']
WARNING:root:Table formatting in PDF is unknown: header=(['Offset: 0x002C'], ['Bit', 'Read/Write', 'Default/Hex', 'Description']), row=['After the burning operation is completed, cancel the power supply of the eFuse power pin.', 'The following table contains acronyms and abbreviations used in this document. ']
WARNING:root:Table formatting in PDF is unknown: header=(['Offset: 0x0028'], ['Bit', 'Read/Write', 'Default/Hex', 'Description']), row=['When initializing the DMA Controller, the bit[2] should be set up.']
WARNING:root:Table formatting in PDF is unknown: header=([], ['Register_Name', 'Offset', 'Description']), row=['DMAC_EN_REGN ', '0x0100 + N*0x0040  DMAC Channel Enable Register N (N = 0 to 15) ']
WARNING:root:Table formatting in PDF is unknown: header=([], ['Register_Name', 'Offset', 'Description']), row=['DMAC_PAU_REGN ', '0x0104 + N*0x0040  DMAC Channel Pause Register N (N = 0 to 15) ']
WARNING:root:Table formatting in PDF is unknown: header=([], ['Register_Name', 'Offset', 'Description']), row=['DMAC_DESC_ADDR_REGN ', '0x0108 + N*0x0040  DMAC Channel Start Address Register N (N = 0 to 15) ']
WARNING:root:Table formatting in PDF is unknown: header=([], ['Register_Name', 'Offset', 'Description']), row=['DMAC_CFG_REGN ', '0x010C + N*0x0040  DMAC Channel Configuration Register N (N = 0 to 15) ']
WARNING:root:Table formatting in PDF is unknown: header=([], ['Register_Name', 'Offset', 'Description']), row=['DMAC_CUR_SRC_REGN ', '0x0110 + N*0x0040  DMAC Channel Current Source Register N (N = 0 to 15) ']
WARNING:root:Table formatting in PDF is unknown: header=([], ['Register_Name', 'Offset', 'Description']), row=['DMAC_PARA_REGN ', '0x011C + N*0x0040  DMAC Channel Parameter Register N (N = 0 to 15) ']
WARNING:root:Table formatting in PDF is unknown: header=([], ['Register_Name', 'Offset', 'Description']), row=['DMAC_MODE_REGN ', '0x0128 + N*0x0040  DMAC Mode Register N (N = 0 to 15) ']
WARNING:root:Table formatting in PDF is unknown: header=([], ['Register_Name', 'Offset', 'Description']), row=['DMAC_PKG_NUM_REGN ', '0x0130 + N*0x0040  DMAC Package Number Register N (N = 0 to 15) ']
WARNING:root:Table formatting in PDF is unknown: header=([], ['Register_Name', 'Offset', 'Description']), row=['DSP_BOOT_RAMMAP_REG  0x0008 ', 'DSP Boot SRAM Remap Control Register ']
WARNING:root:Table formatting in PDF is unknown: header=([], ['Register_Name', 'Offset', 'Description']), row=['EMAC_TX_DMA_DESC_LIST  0x0020 ', 'EMAC Transmit Descriptor List Address Register ']
WARNING:root:Table formatting in PDF is unknown: header=([], ['Register_Name', 'Offset', 'Description']), row=['EMAC_RX_DMA_DESC_LIST  0x0034 ', 'EMAC Receive Descriptor List Address Register ']
WARNING:root:Did not find proper header for (['Offset: 0x0084'], []) [['31:21 ', 'R ', '0x0 ', '/ ', '20 ', 'R/W ', '0x0 ', 'FSOUT_GATE ', 'fsout Clock Gate Enable Control ', '0: Gated ', '1: Not gated ', '19:16 ', 'R/W ', '0x0 ', 'FSOUT_CLK_SRC_SEL ', 'fsout Clock Source Select ', '00: I2S0_ASRC_CLK ', '01: ACLK ', '10: ACLKM ', '11: BCLK ', 'Others: Reserved ', '15:8 ', '/ ', '/ ', '/ ', '7:4 ', 'R/W ', '0x0 ', 'FSOUT_CLK_FREQ_DIV_COE1 ', 'fsout Frequency Division Coefficient 1 ', 'The First Division Factor ', 'It has two levels of frequency division, the first level is bit[7:4], ', 'the second level is bit[3:0], and the frequency division factors ', 'are  multiplied  by  the  two  division  factors,  the  division ', 'relationship of the two divisions are the same. ', '4’d0 = Res (no output),   ', '4’d1 = 1x,   ', '4’d2 = 1/2x,   ', '4’d3 = 1/4x,   ', '4’d4 = 1/6x,   ', '4’d5 = 1/8x,   ', '4’d6 = 1/12x,   ', '4’d7 = 1/16x,   ', '4’d8 = 1/24x,   ', '4’d9 = 1/32x,   ', '4’d10 = 1/48,   ', '4’d11 = 1/64x,   ', '4’d12 = 1/96x,   ', '4’d13 = 1/128x,   ', '4’d14 = 1/176x,   ', '4’d15 = 1/192x ', '3:0 ', 'R/W ', '0x0 ', 'FSOUT_CLK_FREQ_DIV_COE2 ', 'fsout Frequency Division Coefficient 2 ', 'The Second Division Factor ', '4’d0 = Res (no output),   ', '4’d1 = 1x,   ', '4’d2 = 1/2x,   ', '4’d3 = 1/4x,   ', '4’d4 = 1/6x,   ', '4’d5 = 1/8x,   ', '4’d6 = 1/12x,   ', '4’d7 = 1/16x,   ', '4’d8 = 1/24x,   ', '4’d9 = 1/32x,   ', '4’d10 = 1/48,   ', '4’d11 = 1/64x,   ', '4’d12 = 1/96x,   ', '4’d13 = 1/128x,   ', '4’d14 = 1/176x,   ', '4’d15 = 1/192x ', ' ']] None.
WARNING:root:Table formatting in PDF is unknown: header=(['Offset: 0x0030'], ['Bit', 'Read/Write', 'Default/Hex', 'Description']), row=['HSTimer0 is a 56-bit counter. The current value consists of two parts: HS_TMR0_CUR_VALUE_LO acts as the']
WARNING:root:Table formatting in PDF is unknown: header=(['Offset: 0x0030'], ['Bit', 'Read/Write', 'Default/Hex', 'Description']), row=['bit[31:0]  and  HS_TMR0_CUR_VALUE_HI  acts  as  the  bit[55:32].  To  read  or  write  the  current  value,']
WARNING:root:Table formatting in PDF is unknown: header=(['Offset: 0x0030'], ['Bit', 'Read/Write', 'Default/Hex', 'Description']), row=['HS_TMR0_CUR_VALUE_LO should be done before HS_TMR0_CUR_VALUE_HI.']
WARNING:root:Table formatting in PDF is unknown: header=(['Offset: 0x0028'], ['Bit', 'Read/Write', 'Default/Hex', 'Description']), row=['HSTimer0 is a 56-bit counter. The interval value consists of two parts: HS_TMR0_INTV_VALUE_LO acts as']
WARNING:root:Table formatting in PDF is unknown: header=(['Offset: 0x0028'], ['Bit', 'Read/Write', 'Default/Hex', 'Description']), row=['the  bit[31:0]  and  HS_TMR0_INTV_VALUE_HI  acts  as  the  bit[55:32].  To  read  or  write  the  interval  value,']
WARNING:root:Table formatting in PDF is unknown: header=(['Offset: 0x0028'], ['Bit', 'Read/Write', 'Default/Hex', 'Description']), row=['HS_TMR0_INTV_LO_REG should be done before HS_TMR0_INTV_HI_REG.']
WARNING:root:Table formatting in PDF is unknown: header=(['Offset: 0x0050'], ['Bit', 'Read/Write', 'Default/Hex', 'Description']), row=['HSTimer1 is a 56-bit counter. The current value consists of two parts: HS_TMR1_CUR_VALUE_LO acts as the']
WARNING:root:Table formatting in PDF is unknown: header=(['Offset: 0x0050'], ['Bit', 'Read/Write', 'Default/Hex', 'Description']), row=['bit[31:0]  and  HS_TMR1_CUR_VALUE_HI  acts  as  the  bit[55:32].  To  read  or  write  the  current  value,']
WARNING:root:Table formatting in PDF is unknown: header=(['Offset: 0x0050'], ['Bit', 'Read/Write', 'Default/Hex', 'Description']), row=['HS_TMR1_CUR_VALUE_LO should be done before HS_TMR1_CUR_VALUE_HI.']
WARNING:root:Table formatting in PDF is unknown: header=(['Offset: 0x0048'], ['Bit', 'Read/Write', 'Default/Hex', 'Description']), row=['HSTimer1 is a 56-bit counter. The interval value consists of two parts: HS_TMR1_INTV_VALUE_LO acts as']
WARNING:root:Table formatting in PDF is unknown: header=(['Offset: 0x0048'], ['Bit', 'Read/Write', 'Default/Hex', 'Description']), row=['the  bit[31:0]  and  HS_TMR1_INTV_VALUE_HI  acts  as  the  bit[55:32].  To  read  or  write  the  interval  value,']
WARNING:root:Table formatting in PDF is unknown: header=(['Offset: 0x0048'], ['Bit', 'Read/Write', 'Default/Hex', 'Description']), row=['HS_TMR1_INTV_LO_REG should be done before HS_TMR1_INTV_HI_REG.']
WARNING:root:Table formatting in PDF is unknown: header=([], ['Register_Name', 'Offset', 'Description']), row=['MSGBOX_WR_INT_THRESHOLD_']
WARNING:root:Table formatting in PDF is unknown: header=([], ['Register_Name', 'Offset', 'Description']), row=['PLIC_PRIO_REGn ', '0x0000+n*0x0004 (0<n<256)  PLIC Priority Register n ']
WARNING:root:Table formatting in PDF is unknown: header=(['Offset: 0x0010'], ['Bit', 'Read/Write', 'Default/Hex', 'Description']), row=['31:8 ', '/', '/ ']
WARNING:root:Table formatting in PDF is unknown: header=(['Offset: 0x001C'], ['Bit', 'Read/Write', 'Default/Hex', 'Description']), row=['31:8 ', '/', '/ ']
WARNING:root:Table formatting in PDF is unknown: header=([], ['Register_Name', 'Offset', 'Description']), row=['SPINLOCK_LOCK_REGN ', '0x0100 + N*0x0004  Spinlock Register N (N = 0 to 31) ']
WARNING:root:Table formatting in PDF is unknown: header=(['Offset: 0x0080'], ['Bit', 'Read/Write', 'Default/Hex', 'Description']), row=['31:0', 'R ', '0x77777777  LOCKID0 ']
WARNING:root:Table formatting in PDF is unknown: header=(['Offset: 0x0084'], ['Bit', 'Read/Write', 'Default/Hex', 'Description']), row=['31:0', 'R ', '0x77777777  LOCKID1 ']
WARNING:root:Table formatting in PDF is unknown: header=(['Offset: 0x0088'], ['Bit', 'Read/Write', 'Default/Hex', 'Description']), row=['31:0', 'R ', '0x77777777  LOCKID2 ']
WARNING:root:Table formatting in PDF is unknown: header=(['Offset: 0x008C'], ['Bit', 'Read/Write', 'Default/Hex', 'Description']), row=['31:0', 'R ', '0x77777777  LOCKID3 ']
WARNING:root:Table formatting in PDF is unknown: header=(['Offset: 0x0090'], ['Bit', 'Read/Write', 'Default/Hex', 'Description']), row=['31:0', 'R ', '0x77777777  LOCKID4 ']
WARNING:root:Table formatting in PDF is unknown: header=(['Offset: 0x0014'], ['Bit', 'Read/Write', 'Default/Hex', 'Description']), row=['Take the system clock and timer clock source into consideration when setting the interval value.']
WARNING:root:Table formatting in PDF is unknown: header=(['Offset: 0x0024'], ['Bit', 'Read/Write', 'Default/Hex', 'Description']), row=['Take the system clock and timer clock source into consideration when setting the interval value.']
WARNING:root:Table formatting in PDF is unknown: header=([], ['Register_Name', 'Offset', 'Description']), row=['TVD_TOP ']
WARNING:root:Table formatting in PDF is unknown: header=([], ['Register_Name', 'Offset', 'Description']), row=['TVE_TOP ']
WARNING:root:Table formatting in PDF is unknown: header=([], ['Register_Name', 'Offset', 'Description']), row=['TV_CEU_COEF_MUL_REG ', '0x0110+N*0x04(N=0–10)  TV CEU Coefficient Register0 ']
WARNING:root:Table formatting in PDF is unknown: header=(['Offset: 0x0000'], ['Bit', 'Read/Write', 'Default/Hex', 'Description']), row=['For 7-bit addressing:']
WARNING:root:Table formatting in PDF is unknown: header=(['Offset: 0x0000'], ['Bit', 'Read/Write', 'Default/Hex', 'Description']), row=['SLA6 – SLA0 is the 7-bit address of the TWI in slave mode. When the TWI receives this address after a START']
WARNING:root:Table formatting in PDF is unknown: header=(['Offset: 0x0000'], ['Bit', 'Read/Write', 'Default/Hex', 'Description']), row=['condition, it will generate an interrupt and enter slave mode. (SLA6  corresponds to the first bit received']
WARNING:root:Table formatting in PDF is unknown: header=(['Offset: 0x0000'], ['Bit', 'Read/Write', 'Default/Hex', 'Description']), row=['from the TWI bus.) If GCE is set to ‘1’, the TWI will also recognize the general call address (00h).']
WARNING:root:Table formatting in PDF is unknown: header=(['Offset: 0x0000'], ['Bit', 'Read/Write', 'Default/Hex', 'Description']), row=['For 10-bit addressing:']
WARNING:root:Table formatting in PDF is unknown: header=(['Offset: 0x0000'], ['Bit', 'Read/Write', 'Default/Hex', 'Description']), row=['When  the  address  received  starts  with b’11110,  the  TWI  recognizes b’11110  as  the  first  part  of  a 10-bit']
WARNING:root:Table formatting in PDF is unknown: header=(['Offset: 0x0000'], ['Bit', 'Read/Write', 'Default/Hex', 'Description']), row=['address and if the next two bits match ADDR[2:1] (For example, SLAX9 and SLAX8 for the extended address']
WARNING:root:Table formatting in PDF is unknown: header=(['Offset: 0x0000'], ['Bit', 'Read/Write', 'Default/Hex', 'Description']), row=['of the device), it sends an ACK. (The device does not generate an interrupt at this point.) If the next byte of']
WARNING:root:Table formatting in PDF is unknown: header=(['Offset: 0x0000'], ['Bit', 'Read/Write', 'Default/Hex', 'Description']), row=['the address matches the XADDR register (SLAX7 – SLAX0), the TWI generates an interrupt and goes into slave']
WARNING:root:Table formatting in PDF is unknown: header=(['Offset: 0x0000'], ['Bit', 'Read/Write', 'Default/Hex', 'Description']), row=['mode.']
WARNING:root:Table formatting in PDF is unknown: header=([], ['Register_Name', 'Offset', 'Description']), row=['TWI_DRV_SEND_FIFO_ACC  0x0300 ', 'TWI_DRV Send Data FIFO Access Register ']
WARNING:root:Table formatting in PDF is unknown: header=([], ['Register_Name', 'Offset', 'Description']), row=['TWI_DRV_RECV_FIFO_ACC  0x0304 ', 'TWI_DRV Receive Data FIFO Access Register ']
WARNING:root:register 'ADC1_REG' field 'ADC1_PGA_GAIN_CTRL' enum variants are not unique ([('0x0', ' 0 dB    '), ('0x10', ' 21 dB   '), ('0x1', ' 6 dB    '), ('0x11', ' 22 dB   '), ('0x2', ' 6 dB    '), ('0x12', ' 23 dB   '), ('0x3', ' 6 dB    '), ('0x13', ' 24 dB   '), ('0x4', ' 9 dB    '), ('0x14', ' 25 dB   '), ('0x5', ' 10 dB  '), ('0x15', ' 26 dB   '), ('0x6', ' 11 dB  '), ('0x16', ' 27 dB   '), ('0x7', ' 12 dB  '), ('0x17', ' 28 dB   '), ('0x8', ' 13 dB  '), ('0x18', ' 29 dB   '), ('0x9', ' 14 dB  '), ('0x19', ' 30 dB   '), ('0xA', ' 15 dB  '), ('0x1A', ' 31 dB   '), ('0xB', ' 16 dB  '), ('0x1B', ' 32 dB   '), ('0xC', ' 17 dB  '), ('0x1C', ' 33 dB   '), ('0xD', ' 18 dB  '), ('0x1D', ' 34 dB   '), ('0xE', ' 19 dB  '), ('0x1E', ' 35 dB   '), ('0xF', ' 20 dB  '), ('0x1F', ' 36 dB   ')], counter = 3). Giving up.
WARNING:root:register 'ADC2_REG' field 'ADC2_PGA_GAIN_CTRL' enum variants are not unique ([('0x0', ' 0 dB    '), ('0x10', ' 21 dB   '), ('0x1', ' 6 dB    '), ('0x11', ' 22 dB   '), ('0x2', ' 6 dB    '), ('0x12', ' 23 dB   '), ('0x3', ' 6 dB    '), ('0x13', ' 24 dB   '), ('0x4', ' 9 dB    '), ('0x14', ' 25 dB   '), ('0x5', ' 10 dB  '), ('0x15', ' 26 dB   '), ('0x6', ' 11 dB  '), ('0x16', ' 27 dB   '), ('0x7', ' 12 dB  '), ('0x17', ' 28 dB   '), ('0x8', ' 13 dB  '), ('0x18', ' 29 dB   '), ('0x9', ' 14 dB  '), ('0x19', ' 30 dB   '), ('0xA', ' 15 dB  '), ('0x1A', ' 31 dB   '), ('0xB', ' 16 dB  '), ('0x1B', ' 32 dB   '), ('0xC', ' 17 dB  '), ('0x1C', ' 33 dB   '), ('0xD', ' 18 dB  '), ('0x1D', ' 34 dB   '), ('0xE', ' 19 dB  '), ('0x1E', ' 35 dB   '), ('0xF', ' 20 dB  '), ('0x1F', ' 36 dB   ')], counter = 3). Giving up.
WARNING:root:register 'ADC3_REG' field 'ADC3_PGA_GAIN_CTRL' enum variants are not unique ([('0x0', ' 0 dB    '), ('0x10', ' 21 dB   '), ('0x1', ' 6 dB    '), ('0x11', ' 22 dB   '), ('0x2', ' 6 dB    '), ('0x12', ' 23 dB   '), ('0x3', ' 6 dB    '), ('0x13', ' 24 dB   '), ('0x4', ' 9 dB    '), ('0x14', ' 25 dB   '), ('0x5', ' 10 dB  '), ('0x15', ' 26 dB   '), ('0x6', ' 11 dB  '), ('0x16', ' 27 dB   '), ('0x7', ' 12 dB  '), ('0x17', ' 28 dB   '), ('0x8', ' 13 dB  '), ('0x18', ' 29 dB   '), ('0x9', ' 14 dB  '), ('0x19', ' 30 dB   '), ('0xA', ' 15 dB  '), ('0x1A', ' 31 dB   '), ('0xB', ' 16 dB  '), ('0x1B', ' 32 dB   '), ('0xC', ' 17 dB  '), ('0x1C', ' 33 dB   '), ('0xD', ' 18 dB  '), ('0x1D', ' 34 dB   '), ('0xE', ' 19 dB  '), ('0x1E', ' 35 dB   '), ('0xF', ' 20 dB  '), ('0x1F', ' 36 dB   ')], counter = 3). Giving up.
WARNING:root:register 'AC_DAC_DG' field 'ADDA_LOOP_MODE' enum variants are not unique ([('000', ' Disabled '), ('001', ' ADDA LOOP MODE DACL/DACR is connected to ADC1/ADC2 '), ('010', ' ADDA LOOP MODE DACL/DACR is connected to ADC3'), ('Others', ' Reserved   ')], counter = 2). Giving up.
WARNING:root:'RTC_SPI_CLK_CTRL_REG': Field names are not unique: ['RTC', 'RTC']
WARNING:root:'_32K_FOUT_CTRL_GATING_REG': Field name could not be determined: ['0', 'R/W ', '0x0 ', '32K_FANOUT_GATING  LOSC out gating enable  Configuration of LOSC output, and there is no LOSC output by  default. \n0: Mask LOSC output gating \n1: Enable LOSC output gating   '] (tried: '')
INFO:root:'RTC': Register block: None: {'ALARM0_CUR_VLU_REG': [36], 'ALARM0_DAY_SET_REG': [32], 'ALARM0_ENABLE_REG': [40], 'ALARM0_IRQ_EN': [44], 'ALARM0_IRQ_STA_REG': [48], 'ALARM_CONFIG_REG': [80], 'DCXO_CTRL_REG': [352], 'EFUSE_HV_PWRSWT_CTRL_REG': [516], 'FBOOT_INFO_REG0': [288], 'FBOOT_INFO_REG1': [292], 'IC_CHARA_REG': [496], 'INTOSC_CLK_PRESCAL_REG': [8], 'LOSC_AUTO_SWT_STA_REG': [4], 'LOSC_CTRL_REG': [0], 'RTC_DAY_REG': [16], 'RTC_HH_MM_SS_REG': [20], 'RTC_SPI_CLK_CTRL_REG': [784], 'RTC_VIO_REG': [400], 'VDD_OFF_GATING_CTRL_REG': [500], '_32K_FOUT_CTRL_GATING_REG': [96]}
INFO:root:'RTC': Register block: ('N', (0, 1, 2, 3, 4, 5, 6, 7)): {'GP_DATA_REGN': [256, 260, 264, 268, 272, 276, 280, 284]}
WARNING:root:register 'VDD_OFF_GATING_CTRL_REG' field 'VCCIO_DET_SPARE' enum variants are not unique ([['0', ' Disable VCC-IO detection '], ['1', ' Force the detection output  Bit[2:0]: Gear adjustment '], ['000', ' Detection threshold is 2.5 V '], ['001', ' Detection threshold is 2.6 V '], ['010', ' Detection threshold is 2.7 V (default) '], ['011', ' Detection threshold is 2.8 V '], ['100', ' Detection threshold is 2.9 V '], ['101', ' Detection threshold is 3 V '], ['110', ' N/A '], ['111', ' N/A ']], counter = 2). Giving up.
WARNING:root:Could not interpret enumeratedValue '00': 'PLL_AUDIO0(1X)' in field 'CLK_SRC_SE' in register 'AUDIO_CODEC_ADC_CLK_REG' (num_bits = 3)
WARNING:root:Could not interpret enumeratedValue '01': 'PLL_AUDIO1(DIV2)' in field 'CLK_SRC_SE' in register 'AUDIO_CODEC_ADC_CLK_REG' (num_bits = 3)
WARNING:root:Could not interpret enumeratedValue '10': 'PLL_AUDIO1(DIV5)' in field 'CLK_SRC_SE' in register 'AUDIO_CODEC_ADC_CLK_REG' (num_bits = 3)
WARNING:root:Could not interpret enumeratedValue '00': 'PLL_AUDIO0(1X)' in field 'CLK_SRC_SE' in register 'AUDIO_CODEC_DAC_CLK_REG' (num_bits = 3)
WARNING:root:Could not interpret enumeratedValue '01': 'PLL_AUDIO1(DIV2)' in field 'CLK_SRC_SE' in register 'AUDIO_CODEC_DAC_CLK_REG' (num_bits = 3)
WARNING:root:Could not interpret enumeratedValue '10': 'PLL_AUDIO1(DIV5)' in field 'CLK_SRC_SE' in register 'AUDIO_CODEC_DAC_CLK_REG' (num_bits = 3)
WARNING:root:Could not interpret enumeratedValue '00': 'HOSC' in field 'CLK_SRC_SEL' in register 'CE_CLK_REG' (num_bits = 3)
WARNING:root:Could not interpret enumeratedValue '01': 'PLL_PERI(2X)' in field 'CLK_SRC_SEL' in register 'CE_CLK_REG' (num_bits = 3)
WARNING:root:Could not interpret enumeratedValue '10': 'PLL_PERI(1X)' in field 'CLK_SRC_SEL' in register 'CE_CLK_REG' (num_bits = 3)
WARNING:root:Could not interpret enumeratedValue '000': 'PLL_VIDEO0(1X)' in field 'CLK27M_SCR_SEL' in register 'CLK27M_FAN_REG' (num_bits = 2)
WARNING:root:Could not interpret enumeratedValue '001': 'PLL_VIDEO1(1X)' in field 'CLK27M_SCR_SEL' in register 'CLK27M_FAN_REG' (num_bits = 2)
WARNING:root:Could not interpret enumeratedValue '00': 'PLL_AUDIO0(1X)' in field 'CLK_SRC_SEL' in register 'DMIC_CLK_REG' (num_bits = 3)
WARNING:root:Could not interpret enumeratedValue '01': 'PLL_AUDIO1(DIV2)' in field 'CLK_SRC_SEL' in register 'DMIC_CLK_REG' (num_bits = 3)
WARNING:root:Could not interpret enumeratedValue '10': 'PLL_AUDIO1(DIV5)' in field 'CLK_SRC_SEL' in register 'DMIC_CLK_REG' (num_bits = 3)
WARNING:root:Could not interpret enumeratedValue '00': 'PLL_DDR' in field 'DRAM_CLK_SEL' in register 'DRAM_CLK_REG' (num_bits = 3)
WARNING:root:Could not interpret enumeratedValue '01': 'PLL_AUDIO1(DIV2)' in field 'DRAM_CLK_SEL' in register 'DRAM_CLK_REG' (num_bits = 3)
WARNING:root:Could not interpret enumeratedValue '10': 'PLL_PERI(2X)' in field 'DRAM_CLK_SEL' in register 'DRAM_CLK_REG' (num_bits = 3)
WARNING:root:Could not interpret enumeratedValue '11': 'PLL_PERI(800M)' in field 'DRAM_CLK_SEL' in register 'DRAM_CLK_REG' (num_bits = 3)
WARNING:root:Could not interpret enumeratedValue '00': 'PLL_AUDIO0(1X)' in field 'CLK_SRC_SEL' in register 'I2S_PCM0_CLK_REG' (num_bits = 3)
WARNING:root:Could not interpret enumeratedValue '01': 'PLL_AUDIO0(4X)' in field 'CLK_SRC_SEL' in register 'I2S_PCM0_CLK_REG' (num_bits = 3)
WARNING:root:Could not interpret enumeratedValue '10': 'PLL_AUDIO1(DIV2)' in field 'CLK_SRC_SEL' in register 'I2S_PCM0_CLK_REG' (num_bits = 3)
WARNING:root:Could not interpret enumeratedValue '11': 'PLL_AUDIO1(DIV5)' in field 'CLK_SRC_SEL' in register 'I2S_PCM0_CLK_REG' (num_bits = 3)
WARNING:root:Could not interpret enumeratedValue '00': 'PLL_AUDIO0(1X)' in field 'CLK_SRC_SEL' in register 'I2S_PCM1_CLK_REG' (num_bits = 3)
WARNING:root:Could not interpret enumeratedValue '01': 'PLL_AUDIO0(4X)' in field 'CLK_SRC_SEL' in register 'I2S_PCM1_CLK_REG' (num_bits = 3)
WARNING:root:Could not interpret enumeratedValue '10': 'PLL_AUDIO1(DIV2)' in field 'CLK_SRC_SEL' in register 'I2S_PCM1_CLK_REG' (num_bits = 3)
WARNING:root:Could not interpret enumeratedValue '11': 'PLL_AUDIO1(DIV5)' in field 'CLK_SRC_SEL' in register 'I2S_PCM1_CLK_REG' (num_bits = 3)
WARNING:root:Could not interpret enumeratedValue '00': 'PLL_AUDIO0(4X)' in field 'CLK_SRC_SEL' in register 'I2S_PCM2_ASRC_CLK_REG' (num_bits = 3)
WARNING:root:Could not interpret enumeratedValue '01': 'PLL_PERI(1X)' in field 'CLK_SRC_SEL' in register 'I2S_PCM2_ASRC_CLK_REG' (num_bits = 3)
WARNING:root:Could not interpret enumeratedValue '10': 'PLL_AUDIO1(DIV2)' in field 'CLK_SRC_SEL' in register 'I2S_PCM2_ASRC_CLK_REG' (num_bits = 3)
WARNING:root:Could not interpret enumeratedValue '11': 'PLL_AUDIO1(DIV5)' in field 'CLK_SRC_SEL' in register 'I2S_PCM2_ASRC_CLK_REG' (num_bits = 3)
WARNING:root:Could not interpret enumeratedValue '00': 'PLL_AUDIO0(1X)' in field 'CLK_SRC_SEL' in register 'I2S_PCM2_CLK_REG' (num_bits = 3)
WARNING:root:Could not interpret enumeratedValue '01': 'PLL_AUDIO0(4X)' in field 'CLK_SRC_SEL' in register 'I2S_PCM2_CLK_REG' (num_bits = 3)
WARNING:root:Could not interpret enumeratedValue '10': 'PLL_AUDIO1(DIV2)' in field 'CLK_SRC_SEL' in register 'I2S_PCM2_CLK_REG' (num_bits = 3)
WARNING:root:Could not interpret enumeratedValue '11': 'PLL_AUDIO1(DIV5)' in field 'CLK_SRC_SEL' in register 'I2S_PCM2_CLK_REG' (num_bits = 3)
WARNING:root:Could not interpret enumeratedValue '0': 'HOSC' in field 'CLK_SRC_SEL' in register 'IRTX_CLK_REG' (num_bits = 3)
WARNING:root:Could not interpret enumeratedValue '1': 'PLL_PERI(1X)' in field 'CLK_SRC_SEL' in register 'IRTX_CLK_REG' (num_bits = 3)
WARNING:root:Could not interpret enumeratedValue '00': 'PLL_AUDIO0(1X)' in field 'CLK_SRC_SEL' in register 'OWA_TX_CLK_REG' (num_bits = 3)
WARNING:root:Could not interpret enumeratedValue '01': 'PLL_AUDIO0(4X)' in field 'CLK_SRC_SEL' in register 'OWA_TX_CLK_REG' (num_bits = 3)
WARNING:root:Could not interpret enumeratedValue '10': 'PLL_AUDIO1(DIV2)' in field 'CLK_SRC_SEL' in register 'OWA_TX_CLK_REG' (num_bits = 3)
WARNING:root:Could not interpret enumeratedValue '11': 'PLL_AUDIO1(DIV5)' in field 'CLK_SRC_SEL' in register 'OWA_TX_CLK_REG' (num_bits = 3)
WARNING:root:Could not interpret enumeratedValue '1X': '20-30 Clock Cycles' in field 'PLL_UNLOCK_MDSEL' in register 'PLL_AUDIO0_CTRL_REG' (num_bits = 2)
WARNING:root:Could not interpret enumeratedValue '1X': '20-30 Clock Cycles' in field 'PLL_UNLOCK_MDSEL' in register 'PLL_AUDIO1_CTRL_REG' (num_bits = 2)
WARNING:root:Could not interpret enumeratedValue '1X': '20-30 Clock Cycles' in field 'PLL_UNLOCK_MDSEL' in register 'PLL_CPU_CTRL_REG' (num_bits = 2)
WARNING:root:Could not interpret enumeratedValue '1X': '20-30 Clock Cycles' in field 'PLL_UNLOCK_MDSEL' in register 'PLL_DDR_CTRL_REG' (num_bits = 2)
WARNING:root:Could not interpret enumeratedValue '1X': '20-30 Clock Cycles' in field 'PLL_UNLOCK_MDSEL' in register 'PLL_PERI_CTRL_REG' (num_bits = 2)
WARNING:root:Could not interpret enumeratedValue '1X': '20-30 Clock Cycles' in field 'PLL_UNLOCK_MDSEL' in register 'PLL_VE_CTRL_REG' (num_bits = 2)
WARNING:root:Could not interpret enumeratedValue '1X': '20-30 Clock Cycles' in field 'PLL_UNLOCK_MDSEL' in register 'PLL_VIDEO0_CTRL_REG' (num_bits = 2)
WARNING:root:Could not interpret enumeratedValue '1X': '20-30 Clock Cycles' in field 'PLL_UNLOCK_MDSEL' in register 'PLL_VIDEO1_CTRL_REG' (num_bits = 2)
WARNING:root:register 'USB0_CLK_REG' field 'USB0_CLK12M_SEL' enum variants are not unique ([['00', ' 12M divided from 48 MHz '], ['01', ' 12M divided from 24 MHz '], ['10', ' RTC_32K '], ['11', ' / ']], counter = 2). Giving up.
WARNING:root:register 'USB1_CLK_REG' field 'USB1_CLK12M_SEL' enum variants are not unique ([['00', ' 12M divided from 48 MHz '], ['01', ' 12M divided from 24 MHz '], ['10', ' RTC_32K '], ['11', ' / ']], counter = 2). Giving up.
WARNING:root:'FsinEXTCFG': Field names are not all known; for example the one described by: 'The Cycle Number of Pulse Extend  The cycle is BCLK clock and is 1 at least.   '
WARNING:root:Could not interpret enumeratedValue '0': 'No offset  n: Data is offset by n BCLKs to LRCK' in field 'RX_OFFSET' in register 'I2S_PCM_RXCHSEL' (num_bits = 2)
WARNING:root:Could not interpret enumeratedValue '0': 'No offset  n: Data is offset by n BCLKs to LRCK' in field 'TX0_OFFSET' in register 'I2S_PCM_TX0CHSEL' (num_bits = 2)
WARNING:root:Could not interpret enumeratedValue '0': 'Disabled' in field 'TX0_CHEN' in register 'I2S_PCM_TX0CHSEL' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1': 'Enabled' in field 'TX0_CHEN' in register 'I2S_PCM_TX0CHSEL' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0': 'No offset  n: Data is offset by n BCLKs to LRCK' in field 'TX1_OFFSET' in register 'I2S_PCM_TX1CHSEL' (num_bits = 2)
WARNING:root:Could not interpret enumeratedValue '0': 'Disabled' in field 'TX1_CHEN' in register 'I2S_PCM_TX1CHSEL' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1': 'Enabled' in field 'TX1_CHEN' in register 'I2S_PCM_TX1CHSEL' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0': 'No offset  n: Data is offset by n BCLKs to LRCK' in field 'TX2_OFFSET' in register 'I2S_PCM_TX2CHSEL' (num_bits = 2)
WARNING:root:Could not interpret enumeratedValue '0': 'Disabled' in field 'TX2_CHEN' in register 'I2S_PCM_TX2CHSEL' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1': 'Enabled' in field 'TX2_CHEN' in register 'I2S_PCM_TX2CHSEL' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0': 'No offset  n: Data is offset by n BCLKs to LRCK' in field 'TX3_OFFSET' in register 'I2S_PCM_TX3CHSEL' (num_bits = 2)
WARNING:root:Could not interpret enumeratedValue '0': 'Disabled' in field 'TX3_CHEN' in register 'I2S_PCM_TX3CHSEL' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1': 'Enabled' in field 'TX3_CHEN' in register 'I2S_PCM_TX3CHSEL' (num_bits = 16)
WARNING:root:'HCSPARAMS': Field names are not all known; for example the one described by: 'Port Routing Rules  This  field  indicates  the  method  used  by  this  implementation  for  how all ports are mapped to companion controllers. The value of  this field has the following interpretation:  Value  Meaning  0  The  first  N_PCC  ports  are  routed  to  the  lowest  numbered  function  companion  host  controller,  the  next  N_PCC  port  are  routed  to  the  next  lowest  function companion controller, and so on.  1  The port routing is explicitly enumerated by the first  N_PORTS elements of the HCSP-PORTTOUTE array.  This field will always be ‘0’. '
WARNING:root:'HcBulkCurrentED_BCED_': Default 'BulkCurrentED[31:4]' for field ['31:4', 'R/W ', 'R/W  0x0 ', 'BulkCurrentED[31:4] ', 'This is advanced to the next ED after the HC has served the present  one. HC continues processing the list from where it left off in the  last Frame. When it reaches the end of the Bulk list, HC checks the  ControlListFilled  of  HcControl.  If  set,  it  copies  the  content  of  to  and clears the bit. If it is not  set,  it  does  nothing.  HCD  is  only  allowed  to  modify  this  register  when  the  BulkListEnable  of  is  cleared.  When  set,  the  HCD  only  reads  the  instantaneous  value  of  this  register.  This  is  initially set to zero to indicate the end of the Bulk list. '] was not understood
WARNING:root:'HcBulkCurrentED_BCED_': Default 'BulkCurrentED[31:4]' for field ['31:4', 'R/W ', 'R/W  0x0 ', 'BulkCurrentED[31:4] ', 'This is advanced to the next ED after the HC has served the present  one. HC continues processing the list from where it left off in the  last Frame. When it reaches the end of the Bulk list, HC checks the  ControlListFilled  of  HcControl.  If  set,  it  copies  the  content  of  to  and clears the bit. If it is not  set,  it  does  nothing.  HCD  is  only  allowed  to  modify  this  register  when  the  BulkListEnable  of  is  cleared.  When  set,  the  HCD  only  reads  the  instantaneous  value  of  this  register.  This  is  initially set to zero to indicate the end of the Bulk list. '] was not understood
WARNING:root:'HcBulkCurrentED_BCED_': Default 'BulkCurrentED[31:4]' for field ['31:4', 'R/W ', 'R/W  0x0 ', 'BulkCurrentED[31:4] ', 'This is advanced to the next ED after the HC has served the present  one. HC continues processing the list from where it left off in the  last Frame. When it reaches the end of the Bulk list, HC checks the  ControlListFilled  of  HcControl.  If  set,  it  copies  the  content  of  to  and clears the bit. If it is not  set,  it  does  nothing.  HCD  is  only  allowed  to  modify  this  register  when  the  BulkListEnable  of  is  cleared.  When  set,  the  HCD  only  reads  the  instantaneous  value  of  this  register.  This  is  initially set to zero to indicate the end of the Bulk list. '] was not understood
WARNING:root:'HcBulkCurrentED_BCED_': Default 'BulkCurrentED[31:4]' for field ['31:4', 'R/W ', 'R/W  0x0 ', 'BulkCurrentED[31:4] ', 'This is advanced to the next ED after the HC has served the present  one. HC continues processing the list from where it left off in the  last Frame. When it reaches the end of the Bulk list, HC checks the  ControlListFilled  of  HcControl.  If  set,  it  copies  the  content  of  to  and clears the bit. If it is not  set,  it  does  nothing.  HCD  is  only  allowed  to  modify  this  register  when  the  BulkListEnable  of  is  cleared.  When  set,  the  HCD  only  reads  the  instantaneous  value  of  this  register.  This  is  initially set to zero to indicate the end of the Bulk list. '] was not understood
INFO:root:'HcBulkCurrentED_BCED_': Guessed field name 'ADVANCED_TO_THE_NEXT'
WARNING:root:'HcBulkHeadED_BHED_': Field name could not be determined: ['31:4', 'R/W ', 'R ', '0x0 ', 'BHED[31:4]  The  HcBulkHeadED  register  contains  the  physical  address  of  the  first Endpoint Descriptor of the Bulk list. HC traverses the Bulk list  starting  with  the  HcBulkHeadED  pointer.  The  content  is  loaded  from HCCA during the initialization of HC. '] (tried: '')
WARNING:root:'HcBulkHeadED_BHED_': Field name could not be determined: ['3:0', 'R ', 'R ', '0x0 ', 'BHED[3:0]  Because the general TD length is 16 bytes, the memory structure  for the TD must be aligned to a 16-byte boundary. So the lower  bits in the PCED, through bit 0 to bit 3 must be zero in this field.   '] (tried: '')
WARNING:root:'HcControlCurrentED_CCED_': Field name could not be determined: ['31:4', 'R/W ', 'R/W ', '0x0 ', 'CCED[31:4]  The pointer is advanced to the next ED after serving the present  one. HC will continue processing the list from where it left off in  the  last  Frame.  When  it  reaches  the  end  of  the  Control  list,  HC  checks  the  ControlListFilled  of  in  HcCommandStatus.  If  set,  it  copies  the  content  of  HcControlHeadED  to  HcControlCurrentED  and clears the bit. If not set, it does nothing.    HCD  is  allowed  to  modify  this  register  only  when  the  ControlListEnable  of  HcControl  is  cleared.  When  set,  HCD  only  reads the instantaneous value of this register. Initially, this is set  to zero to indicate the end of the Control list. '] (tried: '')
WARNING:root:'HcControlCurrentED_CCED_': Field name could not be determined: ['3:0', 'R ', 'R ', '0x0 ', 'CCED[3:0]   Because the general TD length is 16 bytes, the memory structure  for the TD must be aligned to a 16-byte boundary. So the lower  bits in the PCED, through bit 0 to bit 3 must be zero in this field.   '] (tried: '')
WARNING:root:'HcControlHeadED_CHED_': Field name could not be determined: ['31:4', 'R/W ', 'R ', '0x0 ', 'EHCD[31:4]  The  HcControlHeadED  register  contains  the  physical  address  of  the first Endpoint Descriptor of the Control list. HC traverse the  Control  list  starting  with  the  HcControlHeadED  pointer.  The  content is loaded from HCCA during the initialization of HC. '] (tried: '')
WARNING:root:'HcControlHeadED_CHED_': Field name could not be determined: ['3:0', 'R ', 'R ', '0x0 ', 'EHCD[3:0]   Because the general TD length is 16 bytes, the memory structure  for the TD must be aligned to a 16-byte boundary. So the lower  bits in the PCED, through bit 0 to bit 3 must be zero in this field.   '] (tried: '')
WARNING:root:'HcDoneHead': Field name could not be determined: ['31:4', 'R ', 'R/W ', '0x0 ', 'HcDoneHead[31:4]  When a TD is completed, HC writes the content of  to  the  NextTD  field  of  the  TD.  HC  then  overwrites  the  content  of  with  the  address  of  this  TD.  This  is  set  to  zero  whenever HC writes the content of this register to HCCA. It also  sets the  WritebackDoneHead  of  . '] (tried: '')
WARNING:root:'HcDoneHead': Field name could not be determined: ['3:0', 'R ', 'R ', '0x0 ', 'HcDoneHead[3:0]   Because the general TD length is 16 bytes, the memory structure  for the TD must be aligned to a 16-byte boundary. So the lower  bits in the PCED, through bit 0 to bit 3 must be zero in this field.   '] (tried: '')
WARNING:root:'HcHCCA': Field name could not be determined: ['31:8', 'R/W ', 'R ', '0x0 ', 'HCCA[31:8]  This  is  the  base  address  of  the  Host  Controller  Communication  Area.  This  area  is  used  to  hold  the  control  structures  and  the  Interrupt table that are accessed by both the Host Controller and  the Host Controller Driver. '] (tried: '')
WARNING:root:'HcHCCA': Field name could not be determined: ['7:0', 'R ', 'R ', '0x0 ', 'HCCA[7:0]  The  alignment  restriction  in  HcHCCA  register  is  evaluated  by  examining  the  number  of  zeros  in  the  lower  order  bits.  The  minimum alignment is 256 bytes, therefore, bits 0 through 7 must  always return 0 when read. '] (tried: '')
WARNING:root:'HcPeriodCurrentED_PCED_': Field name could not be determined: ['31:4', 'R ', 'R/W ', '0x0 ', 'PCED[31:4]  This is used by HC to point to the head of one of the Periodec list  which will be processed in the current Frame. The content of this  register is updated by HC after a periodic ED has been processed.  HCD may read the content in determining which ED is currently  being processed at the time of reading. '] (tried: '')
WARNING:root:'HcPeriodCurrentED_PCED_': Field name could not be determined: ['3:0', 'R ', 'R ', '0x0 ', 'PCED[3:0]  Because the general TD length is 16 bytes, the memory structure  for the TD must be aligned to a 16-byte boundary. So the lower  bits in the PCED, through bit 0 to bit 3 must be zero in this field.   '] (tried: '')
WARNING:root:'HcRevision': Default 'RemoteWakeupConnected' for field ['9', 'R/W', 'R/W', 'RemoteWakeupConnected ', 'This bit indicates whether HC supports remote wakeup signaling. If  remote  wakeup  is  supported  and  used  by  the  system,  it  is  the  responsibility  of  system  firmware  to  set  this  bit  during  POST.  HC  clear the bit upon a hardware reset but does not alter it upon a  software  reset.  Remote  wakeup  signaling  of  the  host  system  is  host-bus-specific and is not described in this specification. '] was not understood
WARNING:root:'HcRevision': Default 'HostControllerFunctionalState for USB' for field ['7:6', 'R/W', 'R/W', 'HostControllerFunctionalState for USB ', '00b  USBReset  01b  USBResume  10b  USBOperational  11b  USBSuspend  A  transition  to  USBOperational  from  another  state  causes  SOF  generation to begin 1 ms later. HCD may determine whether HC  has begun sending SOFs by reading the StartoFrame field of    HcInterruptStatus.  This field may be changed by HC only when in the USBSUSPEND  state.  HC  may  move  from  the  USBSUSPEND  state  to  the  USBRESUME  state  after  detecting  the  resume  signaling  from  a  downstream port.  HC enters USBSUSPEND after a software reset, whereas it enters  USBRESET after a hardware reset. The latter also resets the Root  Hub and asserts subsequent reset signaling to downstream ports. '] was not understood
WARNING:root:'HcRevision': Default 'RemoteWakeupConnected' for field ['9', 'R/W', 'R/W', 'RemoteWakeupConnected ', 'This bit indicates whether HC supports remote wakeup signaling. If  remote  wakeup  is  supported  and  used  by  the  system,  it  is  the  responsibility  of  system  firmware  to  set  this  bit  during  POST.  HC  clear the bit upon a hardware reset but does not alter it upon a  software  reset.  Remote  wakeup  signaling  of  the  host  system  is  host-bus-specific and is not described in this specification. '] was not understood
WARNING:root:'HcRevision': Default 'HostControllerFunctionalState for USB' for field ['7:6', 'R/W', 'R/W', 'HostControllerFunctionalState for USB ', '00b  USBReset  01b  USBResume  10b  USBOperational  11b  USBSuspend  A  transition  to  USBOperational  from  another  state  causes  SOF  generation to begin 1 ms later. HCD may determine whether HC  has begun sending SOFs by reading the StartoFrame field of    HcInterruptStatus.  This field may be changed by HC only when in the USBSUSPEND  state.  HC  may  move  from  the  USBSUSPEND  state  to  the  USBRESUME  state  after  detecting  the  resume  signaling  from  a  downstream port.  HC enters USBSUSPEND after a software reset, whereas it enters  USBRESET after a hardware reset. The latter also resets the Root  Hub and asserts subsequent reset signaling to downstream ports. '] was not understood
WARNING:root:'HcRevision': Field names are not all known; for example the one described by: 'RemoteWakeupEnable  This bit is used by HCD to enable or disable the remote wakeup  feature upon the detection of upstream resume signaling. When  this bit is set and the  ResumeDetected  bit in  is  set, a remote wakeup is signaled to the host system. Setting this  bit has no impact on the generation of hardware interrupt. '
WARNING:root:'HcRevision': Default 'RemoteWakeupConnected' for field ['9', 'R/W', 'R/W', 'RemoteWakeupConnected ', 'This bit indicates whether HC supports remote wakeup signaling. If  remote  wakeup  is  supported  and  used  by  the  system,  it  is  the  responsibility  of  system  firmware  to  set  this  bit  during  POST.  HC  clear the bit upon a hardware reset but does not alter it upon a  software  reset.  Remote  wakeup  signaling  of  the  host  system  is  host-bus-specific and is not described in this specification. '] was not understood
WARNING:root:'HcRevision': Default 'HostControllerFunctionalState for USB' for field ['7:6', 'R/W', 'R/W', 'HostControllerFunctionalState for USB ', '00b  USBReset  01b  USBResume  10b  USBOperational  11b  USBSuspend  A  transition  to  USBOperational  from  another  state  causes  SOF  generation to begin 1 ms later. HCD may determine whether HC  has begun sending SOFs by reading the StartoFrame field of    HcInterruptStatus.  This field may be changed by HC only when in the USBSUSPEND  state.  HC  may  move  from  the  USBSUSPEND  state  to  the  USBRESUME  state  after  detecting  the  resume  signaling  from  a  downstream port.  HC enters USBSUSPEND after a software reset, whereas it enters  USBRESET after a hardware reset. The latter also resets the Root  Hub and asserts subsequent reset signaling to downstream ports. '] was not understood
WARNING:root:'HcRevision': Field names are not all known; for example the one described by: 'BulkListEnable  This bit is set to enable the processing of the Bulk list in the next  Frame. If cleared by HCD, the processing of the Bulk list does not  occur  after  the  next  SOF.  HC  checks  this  bit  whenever  it  determines to process the list. When disabled, HCD may modify  the  list.  If  is  pointing  to  an  ED  to  be  removed,  HCD  must  advance  the  pointer  by  updating    before re-enabling processing of the list. '
WARNING:root:'HcRevision': Field names are not all known; for example the one described by: 'ControlListEnable  This bit is set to enable the processing of the Control list in the next  Frame. If cleared by HCD, the processing of the Control list does  not occur after the next SOF. HC must check this bit whenever it  determines to process the list. When disabled, HCD may modify  the list. If  is pointing to an ED to be removed,  HCD  must  advance  the  pointer  by  updating  before re-enabling processing of the list. '
WARNING:root:'HcRevision': Field names are not all known; for example the one described by: 'PeriodicListEnable    This bit is set to enable the processing of periodic list in the next  Frame. If cleared by HCD, processing of the periodic list does not  occur  after  the  next  SOF.  HC  must  check  this  bit  before  it  starts  processing the list. '
INFO:root:'HcRevision': Guessed field name 'HC_SUPPORTS_REMOTE_WAKEUP_SIGNALING'
WARNING:root:'HcRhPortStatus': Default 'PortResetStatusChange' for field ['20', 'R/W ', 'R/W  0x0 ', 'PortResetStatusChange', 'This bit is set at the end of the 10-ms port reset signal. The HCD  writes a ‘1’ to clear this bit. Writing a ‘0’ has no effect.  0  port reset is not complete  1  port reset is complete '] was not understood
WARNING:root:'HcRhPortStatus': Default 'PortResetStatusChange' for field ['20', 'R/W ', 'R/W  0x0 ', 'PortResetStatusChange', 'This bit is set at the end of the 10-ms port reset signal. The HCD  writes a ‘1’ to clear this bit. Writing a ‘0’ has no effect.  0  port reset is not complete  1  port reset is complete '] was not understood
WARNING:root:'HcRhPortStatus': Default 'PortResetStatusChange' for field ['20', 'R/W ', 'R/W  0x0 ', 'PortResetStatusChange', 'This bit is set at the end of the 10-ms port reset signal. The HCD  writes a ‘1’ to clear this bit. Writing a ‘0’ has no effect.  0  port reset is not complete  1  port reset is complete '] was not understood
WARNING:root:'HcRhPortStatus': Default 'PortResetStatusChange' for field ['20', 'R/W ', 'R/W  0x0 ', 'PortResetStatusChange', 'This bit is set at the end of the 10-ms port reset signal. The HCD  writes a ‘1’ to clear this bit. Writing a ‘0’ has no effect.  0  port reset is not complete  1  port reset is complete '] was not understood
WARNING:root:'HcRhPortStatus': Default 'PortResetStatusChange' for field ['20', 'R/W ', 'R/W  0x0 ', 'PortResetStatusChange', 'This bit is set at the end of the 10-ms port reset signal. The HCD  writes a ‘1’ to clear this bit. Writing a ‘0’ has no effect.  0  port reset is not complete  1  port reset is complete '] was not understood
WARNING:root:'HcRhPortStatus': Default 'PortResetStatusChange' for field ['20', 'R/W ', 'R/W  0x0 ', 'PortResetStatusChange', 'This bit is set at the end of the 10-ms port reset signal. The HCD  writes a ‘1’ to clear this bit. Writing a ‘0’ has no effect.  0  port reset is not complete  1  port reset is complete '] was not understood
WARNING:root:'HcRhPortStatus': Field names are not all known; for example the one described by: 'This bit is set at the end of the 10-ms port reset signal. The HCD  writes a ‘1’ to clear this bit. Writing a ‘0’ has no effect.  0  port reset is not complete  1  port reset is complete '
WARNING:root:'HcRhPortStatus': Default 'PortOverCurrentIndicatorChange' for field ['19', 'R/W ', 'R/W  0x0 ', 'PortOverCurrentIndicatorChange ', 'This bit is valid only if overcurrent conditions are reported on a  per-port  basis.  This  bit  is  set  when  Root  Hub  changes  the  PortOverCurrentIndicator  bit.  The HCD writes  a  ‘1’  to  clear  this  bit. Writing a ‘0’ has no effect.  0  no change in  PortOverCurrentIndicator   1  PortOverCurrentIndicator  has changed '] was not understood
WARNING:root:'HcRhPortStatus': Field names are not all known; for example the one described by: 'This bit is valid only if overcurrent conditions are reported on a  per-port  basis.  This  bit  is  set  when  Root  Hub  changes  the  PortOverCurrentIndicator  bit.  The HCD writes  a  ‘1’  to  clear  this  bit. Writing a ‘0’ has no effect.  0  no change in  PortOverCurrentIndicator   1  PortOverCurrentIndicator  has changed '
WARNING:root:'HcRhPortStatus': Default 'PortSuspendStatusChange' for field ['18', 'R/W ', 'R/W  0x0 ', 'PortSuspendStatusChange ', 'This bit is set when the full resume sequence has been completed.  This sequence includes the 20-s resume pulse, LS EOP, and 3-ms  resychronization  delay.  The  HCD  writes  a  ‘1’  to  clear  this  bit.  Writing  a  ‘0’  has  no  effect.  This  bit  is  also  cleared  when  ResetStatusChange  is set.  0  resume is not completed  1  resume completed '] was not understood
WARNING:root:'HcRhPortStatus': Default 'PortEnableStatusChange' for field ['17', 'R/W ', 'R/W  0x0 ', 'PortEnableStatusChange ', 'This bit is set when hardware events cause the  PortEnableStatus  bit to be cleared. Changes from HCD writes do not set this bit. The  HCD writes a ‘1’ to clear this bit. Writing a ‘0’ has no effect. 0  no change in  PortEnableStatus   1  change in  PortEnableStatus  '] was not understood
WARNING:root:'HcRhPortStatus': Default 'ConnectStatusChange' for field ['16', 'R/W ', 'R/W  0x0 ', 'ConnectStatusChange ', 'This bit is set whenever a connect or disconnect event occurs. The  HCD  writes  a  ‘1’  to  clear  this  bit.  Writing  a  ‘0’  has  no  effect.  If  CurrentConnectStatus  is  cleared  when  a  SetPortReset,SetPortEnable ,  or  SetPortSuspend  write  occurs,  this  bit  is  set  to force  the  driver  to  re-evaluate  the  connection  status  since  these writes  should  not  occur  if  the  port  is  disconnected.  0  no change in  PortEnableStatus   1  change in  PortEnableStatus     Note: If the DeviceRemovable[NDP] bit is set, this bit is set only  after a Root Hub reset to inform the system that the device is  attached.  '] was not understood
WARNING:root:'HcRhPortStatus': Field name could not be determined: ['8', 'R/W ', 'R/W  0x1 ', '(read)', 'PortPowerStatus  This bit reflects the port’s power status, regardless of the type of  power switching implemented. This bit is cleared if an overcurrent  condition is detected. HCD sets this bit by writing  SetPortPower   or  SetGlobalPower . HCD clears this bit by writing  ClearPortPower  or  ClearGlobalPower . Which power control switches are enabled  is  determined  by  PowerSwitchingMode   and  PortPortControlMask[ NumberDownstreamPort ] .  In  global  switching  mode( PowerSwitchingMode =0),  only  Set/ClearGlobalPower  controls  this bit. In per-port power switching ( PowerSwitchingMode =1), if  the  PortPowerControlMask[NDP]  bit  for  the  port  is  set,  only  Set/ClearPortPower  commands  are  enabled.  If  the  mask  is  not  set,  only  Set/ClearGlobalPower  commands  are  enabled.  When  port power is disabled,  CurrentConnectStatus ,  PortEnableStatus ,  PortSuspendStatus , and  PortResetStatus  should be reset.  0  port power is off  1  port power is on    (write) SetPortPower   The HCD writes a ‘1’ to set the  PortPowerStatus  bit. Writing a ‘0’  has no effect.    Note:  This  bit  is  always  reads  ‘1b’  if  power  switching  is  not  supported. '] (tried: '')
WARNING:root:'HcRhPortStatus': Field names are not all known; for example the one described by: 'PortEnableStatus  This  bit  indicates  whether  the  port  is  enabled  or  disabled.  The  Root  Hub  may  clear  this  bit  when  an  overcurrent  condition,  disconnect  event,  switched-off  power,  or  operational  bus  error  such  as  babble  is  detected.  This  change  also  causes  PortEnabledStatusChange  to be set. HCD sets this bit by writing  SetPortEnable  and  clears  it  by  writing  ClearPortEnable .  This  bit  cannot be set when  CurrentConnectStatus  is cleared. This bit is  also  set,  if  not  already,  at  the  completion  of  a  port  reset  when  ResetStatusChange  is set or port suspend when  SuspendStatusChange  is set.  0  port is disabled  1  port is enabled    (write) SetPortEnable  The HCD sets  PortEnableStatus  by writing a ‘1’. Writing a ‘0’ has  no effect. If  CurrentConnectStatus  is cleared, this write does not  set  PortEnableStatus ,  but  instead  sets  ConnectStatusChange .  This informs the driver that it attempted to enable a disconnected  Port. '
INFO:root:'HcRhPortStatus': Guessed field name 'FULL_RESUME_SEQUENCE_HAS_BEEN_COMPLETED'
INFO:root:'HcRhPortStatus': Guessed field name 'HARDWARE_EVENTS_CAUSE_THE_PORTENABLESTATUS_BIT'
INFO:root:'HcRhPortStatus': Guessed field name 'WHENEVER_A_CONNECT_OR_DISCONNECT_EVENT'
WARNING:root:'HcRhStatus_Register': Field names are not all known; for example the one described by: 'OverCurrentIndicatorChang  This  bit  is  set  by  hardware  when  a  change  has  occurred  to  the  OverCurrentIndicator  field of this register. The HCD clears this bit  by writing a ‘1’. Writing a ‘0’ has no effect.'
WARNING:root:'HcRhStatus_Register': Default 'OverCurrentIndicator' for field ['1', 'R ', 'R/W  0x0 ', 'OverCurrentIndicator ', 'This bit reports overcurrent conditions when the global reporting  is implemented. When set, an overcurrent condition exists. When  cleared, all power operations are normal.    If  per-port  overcurrent  protection  is  implemented  this  bit  is  always ‘0’ '] was not understood
INFO:root:'HcRhStatus_Register': Guessed field name 'REPORTS_OVERCURRENT_CONDITIONS_WHEN_THE_GLOBAL'
WARNING:root:'PHY_CTRL': Field names are not all known; for example the one described by: 'bist_en_a '
WARNING:root:'PORTSC': Field names are not all known; for example the one described by: 'Line Status  These bits reflect the current logical levels of the D+ (bit11) and D- (bit10) signal lines. These bits are used for detection of low-speed  USB  devices  prior  to  port  reset  and  enable  sequence.  This  read  only  field  is  valid  only  when  the  port  enable  bit  is  zero  and  the  current connect status bit is set to a one.  The encoding of the bits are:  Bit[11:10]  USB State  Interpretation  00b  SE0  Not Low-speed device, perform EHCI  reset.  10b  J-state  Not Low-speed device, perform EHCI  reset.  01b  K-state  Low-speed  device,  release  ownership of port.  11b  Undefined  Not Low-speed device, perform EHCI  reset.  This value of this field is undefined if Port Power is zero. '
WARNING:root:'USBCMD': Field names are not all known; for example the one described by: 'Frame List Size  This  field  is  R/W  only  if  Programmable  Frame  List  Flag  in  the  HCCPARAMS registers is set to a one. This field specifies the size of  the    Frame list. The size the frame list controls which bits in the Frame  Index    Register should be used for the Frame List Current index. Values  mean:  Bits  Meaning  00b  1024 elements(4096bytes)Default value  01b  512 elements(2048byts)  10b  256  elements(1024bytes)For  resource-constrained  condition  11b  reserved  The default value is ‘00b’. '
WARNING:root:'USBINTR': Field names are not all known; for example the one described by: 'Interrupt on Async Advance Enable  When this bit is 1, and the Interrupt on Async Advance bit in the  USBSTS register is 1, the host controller will issue an interrupt at  the  next  interrupt  threshold.  The  interrupt  is  acknowledged  by  software clearing the Interrupt on Async Advance bit. '
WARNING:root:'USBINTR': Field names are not unique: ['HOST_SYSTEM_ERROR_ENABLE_WHEN_THIS', 'FRAME_LIST_ROLLOVER_ENABLE_WHEN_THIS', 'PORT_CHANGE_INTERRUPT_ENABLE_WHEN_THIS', 'USB', 'USB']
WARNING:root:'USBSTS': Field names are not unique: ['ASYNCHRONOUS_SCHEDULE_STATUS_THE_BIT_REPORTS', 'PERIODIC_SCHEDULE_STATUS_THE_BIT_REPORTS', 'RECLAMATION_THIS_IS_A_READ-ONLY_STATUS', 'HC', 'INTERRUPT_ON_ASYNC_ADVANCE_SYSTEM_SOFTWARE', 'HOST_SYSTEM_ERROR_THE_HOST_CONTROLLER', 'FRAME_LIST_ROLLOVER_THE_HOST_CONTROLLER', 'PORT_CHANGE_DETECT_THE_HOST_CONTROLLER', 'USB', 'USB']
WARNING:root:'USB_CTRL': Field name could not be determined: ['18', 'R/W ', '0 ', '1: Within 2 us of the resume-K to SE0 transition \n0: Random time value of the resume-K to SE0 transition '] (tried: '')
WARNING:root:'USB_CTRL': Field names are not unique: ['DMA', 'OHCI', 'PP2VBUS', 'AHB', 'AHB', 'AHB', 'AHB', 'ULPI']
WARNING:root:'USBCMD': field 'ASYNCHRONOUS_SCHEDULE_PARK_MODE_ENABLE': Maybe parse error; description='Asynchronous Schedule Park Mode Enable (OPTIONAL)  If the Asynchronous Park Capability bit in the HCCPARAMS register  is a one, then this bit defaults to a 1 and is R/W. Otherwise the bit  must be a zero and is Read Only. Software uses this bit to enable  or disable Park mode. When this bit is one, Park mode is enabled.  When this bit is zero, Park mode is disabled. '
WARNING:root:register 'USB_SPDCR' field 'PORT' enum variants are not unique ([['00', ' Port Disable when no-se0 detect before SOF '], ['01', ' Port Disable when no-se0 detect before SOF '], ['10', ' No Port Disable when no-se0 detect before SOF '], ['11', ' Port Disable when no-se0 3 time detect before SOF during 8    frames     ']], counter = 8). Giving up.
WARNING:root:[['USB1 ', '0x04200000   ']]: Removing cluster 'OHCI FRAME COUNTER PARTITION REGISTER' since it's empty
WARNING:root:[['USB1 ', '0x04200000   ']]: Removing cluster 'OHCI ROOT HUB PARTITION REGISTER' since it's empty
WARNING:root:[['USB1 ', '0x04200000   ']]: Removing cluster 'EHCI CAPABILITY REGISTER' since it's empty
WARNING:root:[['USB1 ', '0x04200000   ']]: Removing cluster 'OHCI MEMORY POINTER PARTITION REGISTER' since it's empty
WARNING:root:[['USB1 ', '0x04200000   ']]: Removing cluster 'OHCI CONTROL AND STATUS PARTITION REGISTER' since it's empty
WARNING:root:[['USB1 ', '0x04200000   ']]: Removing cluster 'EHCI OPERATIONAL REGISTER' since it's empty
WARNING:root:'TMR0_INTV_VALUE_REG': Invalid field ['Take the system clock and timer clock source into consideration when setting the interval value.', '', '', '']: Bitrange error
WARNING:root:'TMR1_INTV_VALUE_REG': Invalid field ['Take the system clock and timer clock source into consideration when setting the interval value.', '', '', '']: Bitrange error
WARNING:root:Could not interpret enumeratedValue 'Others': 'Reserved  Note: The corresponding clock cycles for the interval value (IV)  depends on the frequency of the clock: Cycles = F  * IV.  For example, to get a interval value of 0.5 second, if the clock  source  is  HOSC_32K  (whose  frequency  is  32  KHz),  the  cycle  number  is  16,000;  if  the  clock  source  is  LOSC_32K  (whose  frequency is 32.768 kHz), the cycle number is 16,384.' in field 'WDOG_INTV_VALUE' in register 'WDOG_MODE_REG' (num_bits = 4)
INFO:root:'PWM': Register block: None: {'CER': [192], 'CIER': [16], 'CISR': [20], 'PCCR01': [32], 'PCCR23': [36], 'PCCR45': [40], 'PCCR67': [44], 'PCGR': [64], 'PDZCR01': [96], 'PDZCR23': [100], 'PDZCR45': [104], 'PDZCR67': [108], 'PER': [128], 'PGR0': [144], 'PGR1': [148], 'PGR2': [152], 'PGR3': [156], 'PIER': [0], 'PISR': [4]}
INFO:root:'PWM': Register block: ('N', (0, 1, 2, 3, 4, 5, 6, 7)): {'CCR': [272, 304, 336, 368, 400, 432, 464, 496], 'CFLR': [280, 312, 344, 376, 408, 440, 472, 504], 'CRLR': [276, 308, 340, 372, 404, 436, 468, 500], 'PCNTR': [264, 296, 328, 360, 392, 424, 456, 488], 'PPR': [260, 292, 324, 356, 388, 420, 452, 484]}
WARNING:root:Could not interpret enumeratedValue '0': '1 cycle' in field 'PWM_ENTIRE_CYCLE' in register 'PPR' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1': '2 cycles  …  N: N+1 cycles  If the register needs to be modified dynamically, the PCLK should  be faster than the PWM CLK.' in field 'PWM_ENTIRE_CYCLE' in register 'PPR' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0': '0 cycle' in field 'PWM_ACT_CYCLE' in register 'PPR' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1': '1 cycle  …  N: N cycles' in field 'PWM_ACT_CYCLE' in register 'PPR' (num_bits = 16)
WARNING:root:'CSIC_DMA_CFG_REG': Field names are not unique: ['PAD_VAL', 'YUV', 'YUV', 'OUTPUT_FMT', 'VFLIP_EN', 'HFLIP_EN', 'FIELD_SEL', 'FPS_DS', 'MIN_SDR_WR_SIZE']
WARNING:root:'PRS_CH3_LINE_TIME_REG': Invalid field ['31:16  RO', '0x0 ', 'PRS_CH3_HBLK_TIME ', 'Time of H Blanking when vsync is valid  The unit is csi_top_clk cycle ']: Bitrange error
WARNING:root:'PRS_NCSI_IF_CFG_REG': Field names are not all known; for example the one described by: 'Source type  Bit 20–23 corresponding to the SRC_TYPEs for channel0–3 \n0: Progressed \n1: Interlaced '
WARNING:root:'PRS_NCSI_IF_CFG_REG': Field names are not all known; for example the one described by: 'YUV (separate syncs): \n00000:  RAW  or  YUV420/YUYV422  (each  cycle  one  component  input)  Others: Reserved      CCIR656 (embedded syncs): \n00100: BT656 1 channel \n01100: BT656 2 channels (All data interleaved in one data bus) \n01110: BT656 4 channels (All data interleaved in one data bus)  Others: Reserved   '
WARNING:root:Could not interpret enumeratedValue '0': 'Unmask' in field 'BIST_DATA_MASK' in register 'CSIC_BIST_DATA_MASK_REG' (num_bits = 32)
WARNING:root:Could not interpret enumeratedValue '1': 'Mask' in field 'BIST_DATA_MASK' in register 'CSIC_BIST_DATA_MASK_REG' (num_bits = 32)
WARNING:root:Could not interpret enumeratedValue '0': 'low' in field 'DATA_STA' in register 'CSIC_PRS_SIGNAL_STA_REG' (num_bits = 24)
WARNING:root:Could not interpret enumeratedValue '1': 'high' in field 'DATA_STA' in register 'CSIC_PRS_SIGNAL_STA_REG' (num_bits = 24)
WARNING:root:Could not interpret enumeratedValue '0': 'no down sample' in field 'CH3_FPS_DS' in register 'PRS_CAP_REG' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue '1': '1/2 fps, only receives the first frame every 2 frames' in field 'CH3_FPS_DS' in register 'PRS_CAP_REG' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue '0': 'no down sample' in field 'CH2_FPS_DS' in register 'PRS_CAP_REG' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue '1': '1/2 fps, only receives the first frame every 2 frames' in field 'CH2_FPS_DS' in register 'PRS_CAP_REG' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue '0': 'no down sample' in field 'CH1_FPS_DS' in register 'PRS_CAP_REG' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue '1': '1/2 fps, only receives the first frame every 2 frames' in field 'CH1_FPS_DS' in register 'PRS_CAP_REG' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue '0': 'no down sample' in field 'CH0_FPS_DS' in register 'PRS_CAP_REG' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue '1': '1/2 fps, only receives the first frame every 2 frames' in field 'CH0_FPS_DS' in register 'PRS_CAP_REG' (num_bits = 4)
WARNING:root:register 'CSIC_DMA_CFG_REG' field 'OUTPUT_FMT' enum variants are not unique ([['0000', ' field-raw-8 '], ['0001', ' field-raw-10 '], ['0010', ' field-raw-12 '], ['0011', ' reserved '], ['0100', ' field-rgb565 '], ['0101', ' field-rgb888 '], ['0110', ' field-prgb888 '], ['0111', ' reserved '], ['1000', ' frame-raw-8 '], ['1001', ' frame-raw-10 '], ['1010', ' frame-raw-12 '], ['1011', ' reserved '], ['1100', ' frame-rgb565 '], ['1101', ' frame-rgb888 '], ['1110', ' frame-prgb888 '], ['1111', ' reserved    When the input format is set to YUV422 '], ['0000', ' field planar YCbCr 422 '], ['0001', ' field planar YCbCr 420 '], ['0010', ' frame planar YCbCr 420 '], ['0011', ' frame planar YCbCr 422 '], ['0100', ' field planar YCbCr 422 UV combined (UV sequence) '], ['0101', ' field planar YCbCr 420 UV combined (UV sequence) '], ['0110', ' frame planar YCbCr 420 UV combined (UV sequence) '], ['0111', ' frame planar YCbCr 422 UV combined (UV sequence) '], ['1000', ' filed planar YCbCr 422 UV combined (VU sequence) '], ['1001', ' field planar YCbCr 420 UV combined (VU sequence) '], ['1010', ' frame planar YCbCr 420 UV combined (VU sequence) '], ['1011', ' frame planar YCbCr 422 UV combined (VU sequence) '], ['1100', ' reserved '], ['1101', ' field YCbCr 400   '], ['1110', ' reserved '], ['1111', ' frame YCbCr 400      When the input format is set to YUV420 '], ['0000', ' reserved '], ['0001', ' field planar YCbCr 420 '], ['0010', ' frame planar YCbCr 420 '], ['0011', ' reserved '], ['0100', ' reserved '], ['0101', ' field planar YCbCr 420 UV combined (UV sequence) '], ['0110', ' frame planar YCbCr 420 UV combined (UV sequence)  0111~1000: reserved '], ['1001', ' field planar YCbCr 420 UV combined (VU sequence) '], ['1010', ' frame planar YCbCr 420 UV combined (VU sequence)  1011~1100: reserved '], ['1101', ' field YCbCr 400   '], ['1110', ' reserved '], ['1111', ' frame YCbCr 400 ']], counter = 2). Giving up.
WARNING:root:Could not interpret enumeratedValue '0': 'no down sample' in field 'FPS_DS' in register 'CSIC_DMA_CFG_REG' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue '1': '1/2 fps, only receives the first frame every 2 frames' in field 'FPS_DS' in register 'CSIC_DMA_CFG_REG' (num_bits = 4)
WARNING:root:register 'CSIC_DMA_CFG_REG' field 'OUTPUT_FMT' enum variants are not unique ([['0000', ' field-raw-8 '], ['0001', ' field-raw-10 '], ['0010', ' field-raw-12 '], ['0011', ' reserved '], ['0100', ' field-rgb565 '], ['0101', ' field-rgb888 '], ['0110', ' field-prgb888 '], ['0111', ' reserved '], ['1000', ' frame-raw-8 '], ['1001', ' frame-raw-10 '], ['1010', ' frame-raw-12 '], ['1011', ' reserved '], ['1100', ' frame-rgb565 '], ['1101', ' frame-rgb888 '], ['1110', ' frame-prgb888 '], ['1111', ' reserved    When the input format is set to YUV422 '], ['0000', ' field planar YCbCr 422 '], ['0001', ' field planar YCbCr 420 '], ['0010', ' frame planar YCbCr 420 '], ['0011', ' frame planar YCbCr 422 '], ['0100', ' field planar YCbCr 422 UV combined (UV sequence) '], ['0101', ' field planar YCbCr 420 UV combined (UV sequence) '], ['0110', ' frame planar YCbCr 420 UV combined (UV sequence) '], ['0111', ' frame planar YCbCr 422 UV combined (UV sequence) '], ['1000', ' filed planar YCbCr 422 UV combined (VU sequence) '], ['1001', ' field planar YCbCr 420 UV combined (VU sequence) '], ['1010', ' frame planar YCbCr 420 UV combined (VU sequence) '], ['1011', ' frame planar YCbCr 422 UV combined (VU sequence) '], ['1100', ' reserved '], ['1101', ' field YCbCr 400   '], ['1110', ' reserved '], ['1111', ' frame YCbCr 400      When the input format is set to YUV420 '], ['0000', ' reserved '], ['0001', ' field planar YCbCr 420 '], ['0010', ' frame planar YCbCr 420 '], ['0011', ' reserved '], ['0100', ' reserved '], ['0101', ' field planar YCbCr 420 UV combined (UV sequence) '], ['0110', ' frame planar YCbCr 420 UV combined (UV sequence)  0111~1000: reserved '], ['1001', ' field planar YCbCr 420 UV combined (VU sequence) '], ['1010', ' frame planar YCbCr 420 UV combined (VU sequence)  1011~1100: reserved '], ['1101', ' field YCbCr 400   '], ['1110', ' reserved '], ['1111', ' frame YCbCr 400 ']], counter = 2). Giving up.
WARNING:root:Could not interpret enumeratedValue '0': 'no down sample' in field 'FPS_DS' in register 'CSIC_DMA_CFG_REG' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue '1': '1/2 fps, only receives the first frame every 2 frames' in field 'FPS_DS' in register 'CSIC_DMA_CFG_REG' (num_bits = 4)
WARNING:root:[['CSIC_CCU ', '0x05800000 '], ['CSIC_TOP ', '0x05800800 '], ['CSIC_PARSER0 ', '0x05801000 '], ['CSIC_DMA0 ', '0x05809000 '], ['CSIC_DMA1 ', '0x05809200   ']]: Registers not used in any peripheral: ['CSIC_BIST_CTRL_REG', 'CSIC_BIST_END_ADDR_REG', 'CSIC_BIST_START_ADDR_REG', 'CSIC_DMA_F2_BUFA_RESULT_REG', 'PRS_CH0_INFMT_REG', 'PRS_CH0_INPUT_PARA0_REG', 'PRS_CH0_INPUT_PARA1_REG', 'PRS_CH0_INPUT_PARA2_REG', 'PRS_CH0_INPUT_PARA3_REG', 'PRS_CH0_INT_EN_REG', 'PRS_CH0_INT_STA_REG', 'PRS_CH0_OUTPUT_HSIZE_REG', 'PRS_CH0_OUTPUT_VSIZE_REG', 'PRS_CH1_INFMT_REG', 'PRS_CH1_INPUT_PARA0_REG', 'PRS_CH1_INPUT_PARA1_REG', 'PRS_CH1_INPUT_PARA2_REG', 'PRS_CH1_INPUT_PARA3_REG', 'PRS_CH1_INT_EN_REG', 'PRS_CH1_INT_STA_REG', 'PRS_CH1_OUTPUT_HSIZE_REG', 'PRS_CH1_OUTPUT_VSIZE_REG', 'PRS_CH2_INFMT_REG', 'PRS_CH2_INPUT_PARA0_REG', 'PRS_CH2_INPUT_PARA1_REG', 'PRS_CH2_INPUT_PARA2_REG', 'PRS_CH2_INPUT_PARA3_REG', 'PRS_CH2_INT_EN_REG', 'PRS_CH2_INT_STA_REG', 'PRS_CH2_OUTPUT_HSIZE_REG', 'PRS_CH2_OUTPUT_VSIZE_REG', 'PRS_CH3_INFMT_REG', 'PRS_CH3_INPUT_PARA0_REG', 'PRS_CH3_INPUT_PARA1_REG', 'PRS_CH3_INPUT_PARA2_REG', 'PRS_CH3_INPUT_PARA3_REG', 'PRS_CH3_INT_EN_REG', 'PRS_CH3_INT_STA_REG', 'PRS_CH3_OUTPUT_HSIZE_REG', 'PRS_CH3_OUTPUT_VSIZE_REG', 'PRS_NCSI_IF_CFG_REG']
WARNING:root:'CE_TPR': Invalid field ['Before performing the burning operation, ensure that the power supply of the eFuse power pin is stable.', '', '', '']: Bitrange error
WARNING:root:'CE_TPR': Invalid field ['After the burning operation is completed, cancel the power supply of the eFuse power pin.', 'The following table contains acronyms and abbreviations used in this document. ', '', '']: Bitrange error
WARNING:root:Could not interpret enumeratedValue 'xxx1': 'Algorithm not support' in field 'TASK_CHANNEL3' in register 'CE_ESR' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue 'xx1x': 'Data length error' in field 'TASK_CHANNEL3' in register 'CE_ESR' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue 'x1xx': 'keysram access error for AES' in field 'TASK_CHANNEL3' in register 'CE_ESR' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue 'xxx1': 'Algorithm not support' in field 'TASK_CHANNEL2' in register 'CE_ESR' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue 'xx1x': 'Data length error' in field 'TASK_CHANNEL2' in register 'CE_ESR' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue 'x1xx': 'keysram access error for AES' in field 'TASK_CHANNEL2' in register 'CE_ESR' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue 'xxx1': 'Algorithm not support' in field 'TASK_CHANNEL1' in register 'CE_ESR' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue 'xx1x': 'Data length error' in field 'TASK_CHANNEL1' in register 'CE_ESR' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue 'x1xx': 'keysram access error for AES' in field 'TASK_CHANNEL1' in register 'CE_ESR' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue 'xxx1': 'Algorithm not support' in field 'TASK_CHANNEL0' in register 'CE_ESR' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue 'xx1x': 'Data length error' in field 'TASK_CHANNEL0' in register 'CE_ESR' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue 'x1xx': 'keysram access error for AES' in field 'TASK_CHANNEL0' in register 'CE_ESR' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue '0': 'Disable' in field 'TASK' in register 'CE_ICR' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue '1': 'Enable' in field 'TASK' in register 'CE_ICR' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue '0': 'Not finished' in field 'TASK' in register 'CE_ISR' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue '1': 'Finished  It indicates whether task is completed.    Write the corresponding channel bit of the register to clear the  end flag.  When the last task in the task chain ends, the operation of the  task chain will end normally. If the task fails in the middle, the  task  chain  will  be  aborted.  The  CE_ISR  register  will  be  automatically  updated  when  it  ends  normally  or  aborts  abnormally.  And  it  is  determined  whether  to  generate  an  interrupt  signal  according  to  the  IE  configuration  (bit31)  of   when the current task ends or aborts.  If  using  interrupt,  after  receiving  the  interrupt,  read  the  corresponding  channel  bit  of  CE_ISR  to  judge  whether  it  ends  successfully or stops failure.  If  not  using  interrupt,  the  CE_ISR  status  register  can  be  continuously queried for the channel bit until the successful end  flag is set or the failure stop flag is set. Write the corresponding  channel bit of the register to clear the end flag.  If  it  fails  to  stop,  you  can  read  the  error  code  on  the  channel  corresponding to the   register.' in field 'TASK' in register 'CE_ISR' (num_bits = 4)
WARNING:root:register 'CIR_RXCFG' field 'NTHR' enum variants are not unique ([['0', ' All samples are recorded into RX FIFO '], ['1', ' If the signal is only one sample duration, it is taken as noise  and discarded. '], ['2', ' If the signal is less than (<=) two sample duration, it is taken  as noise and discarded.  … '], ['61', ' If the signal is less than (<=) sixty-one sample duration, it is  taken as noise and discarded. ']], counter = 8). Giving up.
WARNING:root:Could not interpret enumeratedValue '0': 'No available data in RX FIFO' in field 'RAC' in register 'CIR_RXSTA' (num_bits = 7)
WARNING:root:Could not interpret enumeratedValue '1': '1-byte available data in RX FIFO' in field 'RAC' in register 'CIR_RXSTA' (num_bits = 7)
WARNING:root:register 'CIR_TXINT' field 'TPEI_EN' enum variants are not unique ([['0', ' Disable '], ['1', ' Enable    TUI_EN  Transmitter  FIFO  Underrun  Interrupt  Enable  for  Non-cyclical  Pulse '], ['0', ' Disable '], ['1', ' Enable   ']], counter = 2). Giving up.
WARNING:root:register 'CIR_TXSTA' field 'TPE' enum variants are not unique ([['0', '  Transmissions  of  address,  control  and  data  fields  not  completed '], ['1', ' Transmissions of address, control and data fields completed    TUR  Transmitter FIFO Underrun Flag for Non-cyclical Pulse '], ['0', ' No transmitter FIFO underrun '], ['1', ' Transmitter FIFO underrun  Writing 1 clears this bit.   ']], counter = 5). Giving up.
WARNING:root:'SPI_NDMA_MODE_CTL': Default 17 for field ['7:6', 'R/W ', '0x11 ', 'SPI_ACT_M  SPI NDMA Active Mode \n00: dma_active is low   \n01: dma_active is high \n10: dma_active is controlled by dma_request (DRQ) \n11: dma_active is controlled by controller '] does not fit into slot with bitrange 7:6
WARNING:root:register 'DBI_CTL_0' field 'RGB_SOURCE_FORMAT' enum variants are not unique ([('0000', ' RGB '), ('0001', ' RBG '), ('0010', ' GRB '), ('0011', ' GBR '), ('0100', ' BRG '), ('0101', ' BGR'), ('Others', ' Reserved    When video_source_type is RGB16 (DBI_CTL_0[bit0] = 1) '), ('0000', ' RGB  0001~0100: Reserved '), ('0101', ' BGR '), ('0110', ' GRBG_0 {G[5:3]R[4:0]B[4:0]G[2:0]} '), ('0111', ' GBRG_0 {G[5:3]B[4:0]R[4:0]G[2:0]} '), ('1000', ' GRBG_1 {G[2:0]R[4:0]B[4:0]G[5:3]} '), ('1001', ' GBRG_1 {G[2:0]B[4:0]R[4:0]G[5:3]}  Others: Reserved ')], counter = 2). Giving up.
WARNING:root:register 'DBI_CTL_1' field 'RGB666_FMT' enum variants are not unique ([['00', ' Normal Format '], ['01', ' Special Format for ILITEK '], ['10', ' Special Format for New Vision ']], counter = 3). Giving up.
WARNING:root:Could not interpret enumeratedValue '0': '0 burst' in field 'DBC' in register 'SPI_BCC' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue '1': '1 burst  …  N: N bursts  Cannot be written when XCH=1' in field 'DBC' in register 'SPI_BCC' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue '0': '0 burst' in field 'STC' in register 'SPI_BCC' (num_bits = 24)
WARNING:root:Could not interpret enumeratedValue '1': '1 burst  …  N: N bursts  Cannot be written when XCH=1' in field 'STC' in register 'SPI_BCC' (num_bits = 24)
WARNING:root:Could not interpret enumeratedValue '0': '0 byte in TXFIFO' in field 'TF_CNT' in register 'SPI_FSR' (num_bits = 8)
WARNING:root:Could not interpret enumeratedValue '1': '1 byte in TXFIFO  …' in field 'TF_CNT' in register 'SPI_FSR' (num_bits = 8)
WARNING:root:Could not interpret enumeratedValue '0': '0 byte in RXFIFO' in field 'RF_CNT' in register 'SPI_FSR' (num_bits = 8)
WARNING:root:Could not interpret enumeratedValue '1': '1 byte in RXFIFO  …' in field 'RF_CNT' in register 'SPI_FSR' (num_bits = 8)
WARNING:root:Could not interpret enumeratedValue '0': '0 burst' in field 'MBC' in register 'SPI_MBC' (num_bits = 24)
WARNING:root:Could not interpret enumeratedValue '1': '1 burst  …  N: N bursts  Cannot be written when XCH=1.' in field 'MBC' in register 'SPI_MBC' (num_bits = 24)
WARNING:root:Could not interpret enumeratedValue '0': '0 burst' in field 'MWTC' in register 'SPI_MTC' (num_bits = 24)
WARNING:root:Could not interpret enumeratedValue '1': '1 burst  …  N: N bursts  Cannot be written when XCH=1.' in field 'MWTC' in register 'SPI_MTC' (num_bits = 24)
WARNING:root:register 'SPI_NDMA_MODE_CTL' field 'SPI_ACT_M' enum variants are not unique ([['00', ' dma_active is low   '], ['01', ' dma_active is high '], ['10', ' dma_active is controlled by dma_request (DRQ) '], ['11', ' dma_active is controlled by controller ']], counter = 4). Giving up.
WARNING:root:Could not interpret enumeratedValue '0': 'No wait states inserted  n: n SPI_SCLK wait states inserted  Cannot be written when XCH=1.' in field 'SWC' in register 'SPI_WCR' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue '0': 'No wait states inserted  n: n SPI_SCLK wait states inserted  Cannot be written when XCH=1.' in field 'WCC' in register 'SPI_WCR' (num_bits = 16)
WARNING:root:'DMAC_AUTO_GATE_REG': Invalid field ['When initializing the DMA Controller, the bit[2] should be set up.', '', '', '']: Bitrange error
INFO:root:'DMAC': Register block: None: {'DMAC_AUTO_GATE_REG': [40], 'DMAC_IRQ_EN_REG0': [0], 'DMAC_IRQ_EN_REG1': [4], 'DMAC_IRQ_PEND_REG0': [16], 'DMAC_IRQ_PEND_REG1': [20], 'DMAC_STA_REG': [48]}
INFO:root:'DMAC': Register block: ('N', (0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)): {'DMAC_BCNT_LEFT_REGN': [280, 344, 408, 472, 536, 600, 664, 728, 792, 856, 920, 984, 1048, 1112, 1176, 1240], 'DMAC_CFG_REGN': [268, 332, 396, 460, 524, 588, 652, 716, 780, 844, 908, 972, 1036, 1100, 1164, 1228], 'DMAC_CUR_DEST_REGN': [276, 340, 404, 468, 532, 596, 660, 724, 788, 852, 916, 980, 1044, 1108, 1172, 1236], 'DMAC_CUR_SRC_REGN': [272, 336, 400, 464, 528, 592, 656, 720, 784, 848, 912, 976, 1040, 1104, 1168, 1232], 'DMAC_DESC_ADDR_REGN': [264, 328, 392, 456, 520, 584, 648, 712, 776, 840, 904, 968, 1032, 1096, 1160, 1224], 'DMAC_EN_REGN': [256, 320, 384, 448, 512, 576, 640, 704, 768, 832, 896, 960, 1024, 1088, 1152, 1216], 'DMAC_FDESC_ADDR_REGN': [300, 364, 428, 492, 556, 620, 684, 748, 812, 876, 940, 1004, 1068, 1132, 1196, 1260], 'DMAC_MODE_REGN': [296, 360, 424, 488, 552, 616, 680, 744, 808, 872, 936, 1000, 1064, 1128, 1192, 1256], 'DMAC_PARA_REGN': [284, 348, 412, 476, 540, 604, 668, 732, 796, 860, 924, 988, 1052, 1116, 1180, 1244], 'DMAC_PAU_REGN': [260, 324, 388, 452, 516, 580, 644, 708, 772, 836, 900, 964, 1028, 1092, 1156, 1220], 'DMAC_PKG_NUM_REGN': [304, 368, 432, 496, 560, 624, 688, 752, 816, 880, 944, 1008, 1072, 1136, 1200, 1264]}
WARNING:root:Could not interpret enumeratedValue '0': 'Idle' in field 'DMA_STATUS' in register 'DMAC_STA_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1': 'Busy' in field 'DMA_STATUS' in register 'DMAC_STA_REG' (num_bits = 16)
INFO:root:[('EMAC', '0x04500000   ')]: Automatically adding register 'EMAC_RX_DMA_CUR_DESC' even though it's not mentioned in the summary (note: this is working around a bug in the PDF)
INFO:root:[('EMAC', '0x04500000   ')]: Automatically adding register 'EMAC_TX_DMA_CUR_DESC' even though it's not mentioned in the summary (note: this is working around a bug in the PDF)
INFO:root:[('EMAC', '0x04500000   ')]: Automatically adding register 'EMAC_TX_DMA_CUR_BUF' even though it's not mentioned in the summary (note: this is working around a bug in the PDF)
INFO:root:[('EMAC', '0x04500000   ')]: Automatically adding register 'EMAC_RX_DMA_CUR_BUF' even though it's not mentioned in the summary (note: this is working around a bug in the PDF)
INFO:root:[('EMAC', '0x04500000   ')]: Automatically adding register 'EMAC_TX_DMA_LIST' even though it's not mentioned in the summary (note: this is working around a bug in the PDF)
INFO:root:[('EMAC', '0x04500000   ')]: Automatically adding register 'EMAC_RX_DMA_LIST' even though it's not mentioned in the summary (note: this is working around a bug in the PDF)
INFO:root:'EMAC': Register block: None: {'EMAC_ADDR_HIGH0': [80], 'EMAC_ADDR_LOW0': [84], 'EMAC_BASIC_CTL0': [0], 'EMAC_BASIC_CTL1': [4], 'EMAC_INT_EN': [12], 'EMAC_INT_STA': [8], 'EMAC_MII_CMD': [72], 'EMAC_MII_DATA': [76], 'EMAC_RGMII_STA': [208], 'EMAC_RX_CTL0': [36], 'EMAC_RX_CTL1': [40], 'EMAC_RX_DMA_CUR_BUF': [200], 'EMAC_RX_DMA_CUR_DESC': [196], 'EMAC_RX_DMA_LIST': [52], 'EMAC_RX_DMA_STA': [192], 'EMAC_RX_FRM_FLT': [56], 'EMAC_RX_HASH0': [64], 'EMAC_RX_HASH1': [68], 'EMAC_TX_CTL0': [16], 'EMAC_TX_CTL1': [20], 'EMAC_TX_DMA_CUR_BUF': [184], 'EMAC_TX_DMA_CUR_DESC': [180], 'EMAC_TX_DMA_LIST': [32], 'EMAC_TX_DMA_STA': [176], 'EMAC_TX_FLOW_CTL': [28]}
INFO:root:'EMAC': Register block: ('N', (1, 2, 3, 4, 5, 6, 7)): {'EMAC_ADDR_HIGHN': [88, 96, 104, 112, 120, 128, 136], 'EMAC_ADDR_LOWN': [92, 100, 108, 116, 124, 132, 140]}
WARNING:root:register 'EMAC_RX_FRM_FLT' field 'CTL_FRM_FILTER' enum variants are not unique ([['00', ' Drop all control frames '], ['01', ' Drop all control frames '], ['10', ' Receive all control frames '], ['11', ' Receive all control frames when passing the address filter ']], counter = 5). Giving up.
WARNING:root:[['EMAC ', '0x04500000   ']]: Registers not used in any peripheral: ['EMAC_ADDR_HIGHN', 'EMAC_ADDR_LOWN']
WARNING:root:Could not interpret enumeratedValue '110': 'HS400 speed mode' in field 'CRC_DET_PARA' in register 'SMHC_CSDC' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue '011': 'Other speed mode' in field 'CRC_DET_PARA' in register 'SMHC_CSDC' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue '1x': '8-bit width' in field 'CARD_WID' in register 'SMHC_CTYPE' (num_bits = 2)
WARNING:root:Could not interpret enumeratedValue 'Others': 'Reserved  It  should  be  programmed  the  same  as  the  DMA  controller  multiple  transaction  size.  The  units  for  the  transfer  are  the  DWORD.  A  single  transfer  would  be  signaled  based  on  this  value.  The  value  should  be  sub-multiple  of  (RX_TL  +  1)  and  (FIFO_DEPTH - TX_TL)  Recommended:  FIFO_DEPTH = 256, FIFO_SIZE = 256 * 32 = 1K  MSize = 16, TX_TL = 240, RX_TL = 15' in field 'BSIZE_OF_TRANS' in register 'SMHC_FIFOTH' (num_bits = 3)
WARNING:root:Could not interpret enumeratedValue 'EBE': 'End Bit Error    RTO: Response Timeout    RCRC: Response CRC    SBE: Start Bit Error    DRTO: Data Read Timeout    DCRC: Data CRC for Receive    RE: Response Error    Writing 1 clears this bit.' in field 'ERR_FLAG_SUM' in register 'SMHC_IDST_REG' (num_bits = 1)
WARNING:root:register 'SMHC_NTSR' field 'CMD_SAMPLE_TIMING_PHASE' enum variants are not unique ([['00', ' Sample timing phase offset 90  '], ['01', ' Sample timing phase offset 180  '], ['10', ' Sample timing phase offset 270  '], ['11', ' Ignore ']], counter = 2). Giving up.
WARNING:root:register 'SMHC_STATUS' field 'FSM_STA' enum variants are not unique ([['0000', ' Idle '], ['0001', ' Send init sequence '], ['0010', ' TX CMD start bit '], ['0011', ' TX CMD TX bit '], ['0100', ' TX CMD index + argument '], ['0101', ' TX CMD CRC7 '], ['0110', ' TX CMD end bit '], ['0111', ' RX response start bit '], ['1000', ' RX response IRQ response '], ['1001', ' RX response TX bit '], ['1010', ' RX response CMD index '], ['1011', ' RX response data '], ['1100', ' RX response CRC7 '], ['1101', ' RX response end bit '], ['1110', ' CMD path wait NCC '], ['1111', ' Wait; CMD-to-response turn around ']], counter = 2). Giving up.
WARNING:root:'LCD_CTL_REG': Field names are not all known; for example the one described by: 'Set the interface type of LCD controller. \n00: HV(Sync+DE) \n01: 8080 I/F \n1x: Reserved '
INFO:root:'TCON_LCD0': Register block: None: {'FSYNC_GEN_CTRL_REG': [552], 'FSYNC_GEN_DLY_REG': [556], 'LCD_3D_FIFO_REG': [60], 'LCD_BASIC0_REG': [72], 'LCD_BASIC1_REG': [76], 'LCD_BASIC2_REG': [80], 'LCD_BASIC3_REG': [84], 'LCD_CEU_CTL_REG': [256], 'LCD_CMAP_CTL_REG': [384], 'LCD_CMAP_EVEN0_REG': [408], 'LCD_CMAP_EVEN1_REG': [412], 'LCD_CMAP_ODD0_REG': [400], 'LCD_CMAP_ODD1_REG': [404], 'LCD_CPU_IF_REG': [96], 'LCD_CPU_RD0_REG': [104], 'LCD_CPU_RD1_REG': [108], 'LCD_CPU_TRI0_REG': [352], 'LCD_CPU_TRI1_REG': [356], 'LCD_CPU_TRI2_REG': [360], 'LCD_CPU_TRI3_REG': [364], 'LCD_CPU_TRI4_REG': [368], 'LCD_CPU_TRI5_REG': [372], 'LCD_CPU_WR_REG': [100], 'LCD_CTL_REG': [64], 'LCD_DCLK_REG': [68], 'LCD_DEBUG_REG': [252], 'LCD_FRM_CTL_REG': [16], 'LCD_GCTL_REG': [0], 'LCD_GINT0_REG': [4], 'LCD_GINT1_REG': [8], 'LCD_HV_IF_REG': [88], 'LCD_IO_POL_REG': [136], 'LCD_IO_TRI_REG': [140], 'LCD_LVDS_ANA0_REG': [544], 'LCD_LVDS_IF_REG': [132], 'LCD_SAFE_PERIOD_REG': [496], 'LCD_SLAVE_STOP_POS_REG': [568], 'LCD_SYNC_CTL_REG': [560], 'LCD_SYNC_POS_REG': [564]}
INFO:root:'TCON_LCD0': Register block: ('N', (0, 1, 2)): {'LCD_CEU_COEF_ADD_REG': [284, 300, 316], 'LCD_CEU_COEF_RANG_REG': [320, 324, 328]}
INFO:root:'TCON_LCD0': Register block: ('N', (0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10)): {'LCD_CEU_COEF_MUL_REG': [272, 276, 280, 284, 288, 292, 296, 300, 304, 308, 312]}
INFO:root:'TCON_LCD0': Register block: ('N', (0, 1, 2, 3)): {'LCD_FRM_TAB_REG': [44, 48, 52, 56]}
INFO:root:'TCON_LCD0': Register block: ('N', (0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212, 213, 214, 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228, 229, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, 241, 242, 243, 244, 245, 246, 247, 248, 249, 250, 251, 252, 253, 254, 255)): {'LCD_GAMMA_TABLE_REG': [1024, 1028, 1032, 1036, 1040, 1044, 1048, 1052, 1056, 1060, 1064, 1068, 1072, 1076, 1080, 1084, 1088, 1092, 1096, 1100, 1104, 1108, 1112, 1116, 1120, 1124, 1128, 1132, 1136, 1140, 1144, 1148, 1152, 1156, 1160, 1164, 1168, 1172, 1176, 1180, 1184, 1188, 1192, 1196, 1200, 1204, 1208, 1212, 1216, 1220, 1224, 1228, 1232, 1236, 1240, 1244, 1248, 1252, 1256, 1260, 1264, 1268, 1272, 1276, 1280, 1284, 1288, 1292, 1296, 1300, 1304, 1308, 1312, 1316, 1320, 1324, 1328, 1332, 1336, 1340, 1344, 1348, 1352, 1356, 1360, 1364, 1368, 1372, 1376, 1380, 1384, 1388, 1392, 1396, 1400, 1404, 1408, 1412, 1416, 1420, 1424, 1428, 1432, 1436, 1440, 1444, 1448, 1452, 1456, 1460, 1464, 1468, 1472, 1476, 1480, 1484, 1488, 1492, 1496, 1500, 1504, 1508, 1512, 1516, 1520, 1524, 1528, 1532, 1536, 1540, 1544, 1548, 1552, 1556, 1560, 1564, 1568, 1572, 1576, 1580, 1584, 1588, 1592, 1596, 1600, 1604, 1608, 1612, 1616, 1620, 1624, 1628, 1632, 1636, 1640, 1644, 1648, 1652, 1656, 1660, 1664, 1668, 1672, 1676, 1680, 1684, 1688, 1692, 1696, 1700, 1704, 1708, 1712, 1716, 1720, 1724, 1728, 1732, 1736, 1740, 1744, 1748, 1752, 1756, 1760, 1764, 1768, 1772, 1776, 1780, 1784, 1788, 1792, 1796, 1800, 1804, 1808, 1812, 1816, 1820, 1824, 1828, 1832, 1836, 1840, 1844, 1848, 1852, 1856, 1860, 1864, 1868, 1872, 1876, 1880, 1884, 1888, 1892, 1896, 1900, 1904, 1908, 1912, 1916, 1920, 1924, 1928, 1932, 1936, 1940, 1944, 1948, 1952, 1956, 1960, 1964, 1968, 1972, 1976, 1980, 1984, 1988, 1992, 1996, 2000, 2004, 2008, 2012, 2016, 2020, 2024, 2028, 2032, 2036, 2040, 2044]}
INFO:root:'TCON_LCD0': Register block: ('N', (0, 1, 2, 3, 4, 5)): {'xNx': [20, 24, 28, 32, 36, 40]}
WARNING:root:register 'LCD_3D_FIFO_REG' field '3D_FIFO' enum variants are not unique ([['00', ' Bypass '], ['01', ' Used as normal FIFO '], ['10', ' Used as 3D interlace FIFO '], ['11', ' Reserved   ']], counter = 2). Giving up.
WARNING:root:Could not interpret enumeratedValue '0000': 'in_b0' in field 'OUT_EVEN1' in register 'LCD_CMAP_EVEN0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0001': 'in_g0' in field 'OUT_EVEN1' in register 'LCD_CMAP_EVEN0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0010': 'in_r0' in field 'OUT_EVEN1' in register 'LCD_CMAP_EVEN0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0100': 'in_b1' in field 'OUT_EVEN1' in register 'LCD_CMAP_EVEN0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0101': 'in_g1' in field 'OUT_EVEN1' in register 'LCD_CMAP_EVEN0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0110': 'in_r1' in field 'OUT_EVEN1' in register 'LCD_CMAP_EVEN0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1000': 'in_b2' in field 'OUT_EVEN1' in register 'LCD_CMAP_EVEN0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1001': 'in_g2' in field 'OUT_EVEN1' in register 'LCD_CMAP_EVEN0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1010': 'in_r2' in field 'OUT_EVEN1' in register 'LCD_CMAP_EVEN0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1100': 'in_b3' in field 'OUT_EVEN1' in register 'LCD_CMAP_EVEN0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1101': 'in_g3' in field 'OUT_EVEN1' in register 'LCD_CMAP_EVEN0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1110': 'in_r3' in field 'OUT_EVEN1' in register 'LCD_CMAP_EVEN0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0000': 'in_b0' in field 'OUT_EVEN0' in register 'LCD_CMAP_EVEN0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0001': 'in_g0' in field 'OUT_EVEN0' in register 'LCD_CMAP_EVEN0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0010': 'in_r0' in field 'OUT_EVEN0' in register 'LCD_CMAP_EVEN0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0100': 'in_b1' in field 'OUT_EVEN0' in register 'LCD_CMAP_EVEN0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0101': 'in_g1' in field 'OUT_EVEN0' in register 'LCD_CMAP_EVEN0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0110': 'in_r1' in field 'OUT_EVEN0' in register 'LCD_CMAP_EVEN0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1000': 'in_b2' in field 'OUT_EVEN0' in register 'LCD_CMAP_EVEN0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1001': 'in_g2' in field 'OUT_EVEN0' in register 'LCD_CMAP_EVEN0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1010': 'in_r2' in field 'OUT_EVEN0' in register 'LCD_CMAP_EVEN0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1100': 'in_b3' in field 'OUT_EVEN0' in register 'LCD_CMAP_EVEN0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1101': 'in_g3' in field 'OUT_EVEN0' in register 'LCD_CMAP_EVEN0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1110': 'in_r3' in field 'OUT_EVEN0' in register 'LCD_CMAP_EVEN0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0000': 'in_b0' in field 'OUT_EVEN3' in register 'LCD_CMAP_EVEN1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0001': 'in_g0' in field 'OUT_EVEN3' in register 'LCD_CMAP_EVEN1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0010': 'in_r0' in field 'OUT_EVEN3' in register 'LCD_CMAP_EVEN1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0100': 'in_b1' in field 'OUT_EVEN3' in register 'LCD_CMAP_EVEN1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0101': 'in_g1' in field 'OUT_EVEN3' in register 'LCD_CMAP_EVEN1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0110': 'in_r1' in field 'OUT_EVEN3' in register 'LCD_CMAP_EVEN1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1000': 'in_b2' in field 'OUT_EVEN3' in register 'LCD_CMAP_EVEN1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1001': 'in_g2' in field 'OUT_EVEN3' in register 'LCD_CMAP_EVEN1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1010': 'in_r2' in field 'OUT_EVEN3' in register 'LCD_CMAP_EVEN1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1100': 'in_b3' in field 'OUT_EVEN3' in register 'LCD_CMAP_EVEN1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1101': 'in_g3' in field 'OUT_EVEN3' in register 'LCD_CMAP_EVEN1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1110': 'in_r3' in field 'OUT_EVEN3' in register 'LCD_CMAP_EVEN1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0000': 'in_b0' in field 'OUT_EVEN2' in register 'LCD_CMAP_EVEN1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0001': 'in_g0' in field 'OUT_EVEN2' in register 'LCD_CMAP_EVEN1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0010': 'in_r0' in field 'OUT_EVEN2' in register 'LCD_CMAP_EVEN1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0100': 'in_b1' in field 'OUT_EVEN2' in register 'LCD_CMAP_EVEN1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0101': 'in_g1' in field 'OUT_EVEN2' in register 'LCD_CMAP_EVEN1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0110': 'in_r1' in field 'OUT_EVEN2' in register 'LCD_CMAP_EVEN1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1000': 'in_b2' in field 'OUT_EVEN2' in register 'LCD_CMAP_EVEN1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1001': 'in_g2' in field 'OUT_EVEN2' in register 'LCD_CMAP_EVEN1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1010': 'in_r2' in field 'OUT_EVEN2' in register 'LCD_CMAP_EVEN1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1100': 'in_b3' in field 'OUT_EVEN2' in register 'LCD_CMAP_EVEN1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1101': 'in_g3' in field 'OUT_EVEN2' in register 'LCD_CMAP_EVEN1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1110': 'in_r3' in field 'OUT_EVEN2' in register 'LCD_CMAP_EVEN1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0000': 'in_b0' in field 'OUT_ODD1' in register 'LCD_CMAP_ODD0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0001': 'in_g0' in field 'OUT_ODD1' in register 'LCD_CMAP_ODD0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0010': 'in_r0' in field 'OUT_ODD1' in register 'LCD_CMAP_ODD0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0100': 'in_b1' in field 'OUT_ODD1' in register 'LCD_CMAP_ODD0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0101': 'in_g1' in field 'OUT_ODD1' in register 'LCD_CMAP_ODD0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0110': 'in_r1' in field 'OUT_ODD1' in register 'LCD_CMAP_ODD0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1000': 'in_b2' in field 'OUT_ODD1' in register 'LCD_CMAP_ODD0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1001': 'in_g2' in field 'OUT_ODD1' in register 'LCD_CMAP_ODD0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1010': 'in_r2' in field 'OUT_ODD1' in register 'LCD_CMAP_ODD0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1100': 'in_b3' in field 'OUT_ODD1' in register 'LCD_CMAP_ODD0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1101': 'in_g3' in field 'OUT_ODD1' in register 'LCD_CMAP_ODD0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1110': 'in_r3' in field 'OUT_ODD1' in register 'LCD_CMAP_ODD0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0000': 'in_b0' in field 'OUT_ODD0' in register 'LCD_CMAP_ODD0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0001': 'in_g0' in field 'OUT_ODD0' in register 'LCD_CMAP_ODD0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0010': 'in_r0' in field 'OUT_ODD0' in register 'LCD_CMAP_ODD0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0100': 'in_b1' in field 'OUT_ODD0' in register 'LCD_CMAP_ODD0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0101': 'in_g1' in field 'OUT_ODD0' in register 'LCD_CMAP_ODD0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0110': 'in_r1' in field 'OUT_ODD0' in register 'LCD_CMAP_ODD0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1000': 'in_b2' in field 'OUT_ODD0' in register 'LCD_CMAP_ODD0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1001': 'in_g2' in field 'OUT_ODD0' in register 'LCD_CMAP_ODD0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1010': 'in_r2' in field 'OUT_ODD0' in register 'LCD_CMAP_ODD0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1100': 'in_b3' in field 'OUT_ODD0' in register 'LCD_CMAP_ODD0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1101': 'in_g3' in field 'OUT_ODD0' in register 'LCD_CMAP_ODD0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1110': 'in_r3' in field 'OUT_ODD0' in register 'LCD_CMAP_ODD0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0000': 'in_b0' in field 'OUT_ODD3' in register 'LCD_CMAP_ODD1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0001': 'in_g0' in field 'OUT_ODD3' in register 'LCD_CMAP_ODD1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0010': 'in_r0' in field 'OUT_ODD3' in register 'LCD_CMAP_ODD1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0100': 'in_b1' in field 'OUT_ODD3' in register 'LCD_CMAP_ODD1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0101': 'in_g1' in field 'OUT_ODD3' in register 'LCD_CMAP_ODD1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0110': 'in_r1' in field 'OUT_ODD3' in register 'LCD_CMAP_ODD1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1000': 'in_b2' in field 'OUT_ODD3' in register 'LCD_CMAP_ODD1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1001': 'in_g2' in field 'OUT_ODD3' in register 'LCD_CMAP_ODD1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1010': 'in_r2' in field 'OUT_ODD3' in register 'LCD_CMAP_ODD1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1100': 'in_b3' in field 'OUT_ODD3' in register 'LCD_CMAP_ODD1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1101': 'in_g3' in field 'OUT_ODD3' in register 'LCD_CMAP_ODD1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1110': 'in_r3' in field 'OUT_ODD3' in register 'LCD_CMAP_ODD1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0000': 'in_b0' in field 'OUT_ODD2' in register 'LCD_CMAP_ODD1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0001': 'in_g0' in field 'OUT_ODD2' in register 'LCD_CMAP_ODD1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0010': 'in_r0' in field 'OUT_ODD2' in register 'LCD_CMAP_ODD1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0100': 'in_b1' in field 'OUT_ODD2' in register 'LCD_CMAP_ODD1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0101': 'in_g1' in field 'OUT_ODD2' in register 'LCD_CMAP_ODD1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0110': 'in_r1' in field 'OUT_ODD2' in register 'LCD_CMAP_ODD1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1000': 'in_b2' in field 'OUT_ODD2' in register 'LCD_CMAP_ODD1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1001': 'in_g2' in field 'OUT_ODD2' in register 'LCD_CMAP_ODD1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1010': 'in_r2' in field 'OUT_ODD2' in register 'LCD_CMAP_ODD1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1100': 'in_b3' in field 'OUT_ODD2' in register 'LCD_CMAP_ODD1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1101': 'in_g3' in field 'OUT_ODD2' in register 'LCD_CMAP_ODD1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1110': 'in_r3' in field 'OUT_ODD2' in register 'LCD_CMAP_ODD1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue 'xxx1': '24-bit for DSI' in field 'CPU_MODE' in register 'LCD_CPU_IF_REG' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue '0x': 'Auto' in field 'SYNC_MODE' in register 'LCD_CPU_TRI2_REG'
WARNING:root:register 'LCD_CPU_TRI3_REG' field 'TRI_INT_MODE' enum variants are not unique ([['00', ' Disable '], ['01', ' Counter mode   '], ['10', ' Te rising mode '], ['11', ' Te falling mode ']], counter = 2). Giving up.
WARNING:root:register 'LCD_CTL_REG' field 'LCD_SRC_SEL' enum variants are not unique ([['000', ' DE '], ['001', ' Color Check '], ['010', ' Grayscale Check '], ['011', ' Black by White Check '], ['100', ' Test Data all 0 '], ['101', ' Test Data all 1 '], ['110', ' Reversed '], ['111', ' Gridding Check       ']], counter = 2). Giving up.
WARNING:root:register 'LCD_DCLK_REG' field 'LCD_DCLK_EN' enum variants are not unique ([('0000', ' dclk_en = 0; dclk1_en = 0; dclk2_en = 0; dclkm2_en = 0;                           '), ('0001', ' dclk_en = 1; dclk1_en = 0; dclk2_en = 0; dclkm2_en = 0;                         '), ('0010', ' dclk_en = 1; dclk1_en = 0; dclk2_en = 0; dclkm2_en = 1;                         '), ('0011', ' dclk_en = 1; dclk1_en = 1; dclk2_en = 0; dclkm2_en = 0;                         '), ('0101', ' dclk_en = 1; dclk1_en = 0; dclk2_en = 1; dclkm2_en = 0;                         '), ('1111', ' dclk_en = 1; dclk1_en = 1; dclk2_en = 1; dclkm2_en = 1;  '), ('Others', 'Reversed ')], counter = 2). Giving up.
WARNING:root:register 'LCD_FRM_CTL_REG' field 'LCD_FRM_TEST' enum variants are not unique ([['00', ' FRM '], ['01', ' Half 5-/6-bit, half FRM '], ['10', ' Half 8-bit, half FRM '], ['11', ' Half 8-bit, half 5-/6-bit   ']], counter = 2). Giving up.
WARNING:root:register 'LCD_HV_IF_REG' field 'RGB888_ODD_ORDER' enum variants are not unique ([['00', ' R→G→B '], ['01', ' B→R→G '], ['10', ' G→B→R '], ['11', ' R→G→B ']], counter = 2). Giving up.
WARNING:root:register 'LCD_HV_IF_REG' field 'RGB888_EVEN_ORDER' enum variants are not unique ([['00', ' R→G→B '], ['01', ' B→R→G '], ['10', ' G→B→R '], ['11', ' R→G→B ']], counter = 2). Giving up.
WARNING:root:Could not interpret enumeratedValue '0': 'Normal polarity' in field 'DATA_INV' in register 'LCD_IO_POL_REG' (num_bits = 24)
WARNING:root:Could not interpret enumeratedValue '1': 'Invert the specify output' in field 'DATA_INV' in register 'LCD_IO_POL_REG' (num_bits = 24)
WARNING:root:Could not interpret enumeratedValue '1': 'Disable' in field 'DATA_OUTPUT_TRI_EN' in register 'LCD_IO_TRI_REG' (num_bits = 24)
WARNING:root:Could not interpret enumeratedValue '0': 'Enable' in field 'DATA_OUTPUT_TRI_EN' in register 'LCD_IO_TRI_REG' (num_bits = 24)
WARNING:root:Could not interpret enumeratedValue '0': 'Disable' in field 'LVDS_HPREN_DRV' in register 'LCD_LVDS_ANA0_REG' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue '1': 'Enable' in field 'LVDS_HPREN_DRV' in register 'LCD_LVDS_ANA0_REG' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue '0': 'Normal' in field 'LVDS_REG_PLR' in register 'LCD_LVDS_ANA0_REG' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue '1': 'Reverse' in field 'LVDS_REG_PLR' in register 'LCD_LVDS_ANA0_REG' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue '0': 'Reverse' in field 'LCD_LVDS_DATA_POL' in register 'LCD_LVDS_IF_REG' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue '1': 'Normal' in field 'LCD_LVDS_DATA_POL' in register 'LCD_LVDS_IF_REG' (num_bits = 4)
WARNING:root:register 'LCD_SAFE_PERIOD_REG' field 'SAFE_PERIOD_MODE' enum variants are not unique ([['000', ' unsafe '], ['001', ' safe '], ['010', ' safe at FIFO_CURR_NUM > SAFE_PERIOD_FIFO_NUM '], ['011', ' safe at 2 and safe at sync active '], ['100', ' safe at line   ']], counter = 2). Giving up.
WARNING:root:'GP_CTRL': Invalid field ['31:24  R/', 'W', '0x0   ', 'ADC_FIRST_DLY  ADC First Convert Delay Setting  ADC conversion of each channel is delayed by N samples. ']: Bitrange error
WARNING:root:'HS_TMR0_CURNT_HI_REG': Invalid field ['HSTimer0 is a 56-bit counter. The current value consists of two parts: HS_TMR0_CUR_VALUE_LO acts as the', '', '', '']: Bitrange error
WARNING:root:Field could not be parsed as a bitrange: ['bit[31', '0]  and  HS_TMR0_CUR_VALUE_HI  acts  as  the  bit[55', '32].  To  read  or  write  the  current  value,']
WARNING:root:'HS_TMR0_CURNT_HI_REG': Invalid field ['HS_TMR0_CUR_VALUE_LO should be done before HS_TMR0_CUR_VALUE_HI.', '', '', '']: Bitrange error
WARNING:root:'HS_TMR0_INTV_HI_REG': Invalid field ['HSTimer0 is a 56-bit counter. The interval value consists of two parts: HS_TMR0_INTV_VALUE_LO acts as', '', '', '']: Bitrange error
WARNING:root:Field could not be parsed as a bitrange: ['the  bit[31', '0]  and  HS_TMR0_INTV_VALUE_HI  acts  as  the  bit[55', '32].  To  read  or  write  the  interval  value,']
WARNING:root:'HS_TMR0_INTV_HI_REG': Invalid field ['HS_TMR0_INTV_LO_REG should be done before HS_TMR0_INTV_HI_REG.', '', '', '']: Bitrange error
WARNING:root:'HS_TMR1_CURNT_HI_REG': Invalid field ['HSTimer1 is a 56-bit counter. The current value consists of two parts: HS_TMR1_CUR_VALUE_LO acts as the', '', '', '']: Bitrange error
WARNING:root:Field could not be parsed as a bitrange: ['bit[31', '0]  and  HS_TMR1_CUR_VALUE_HI  acts  as  the  bit[55', '32].  To  read  or  write  the  current  value,']
WARNING:root:'HS_TMR1_CURNT_HI_REG': Invalid field ['HS_TMR1_CUR_VALUE_LO should be done before HS_TMR1_CUR_VALUE_HI.', '', '', '']: Bitrange error
WARNING:root:'HS_TMR1_INTV_HI_REG': Invalid field ['HSTimer1 is a 56-bit counter. The interval value consists of two parts: HS_TMR1_INTV_VALUE_LO acts as', '', '', '']: Bitrange error
WARNING:root:Field could not be parsed as a bitrange: ['the  bit[31', '0]  and  HS_TMR1_INTV_VALUE_HI  acts  as  the  bit[55', '32].  To  read  or  write  the  interval  value,']
WARNING:root:'HS_TMR1_INTV_HI_REG': Invalid field ['HS_TMR1_INTV_LO_REG should be done before HS_TMR1_INTV_HI_REG.', '', '', '']: Bitrange error
WARNING:root:Could not interpret enumeratedValue '0': 'High-level trigger' in field 'IRQ_MD0' in register 'IRQ_MODE0_REG' (num_bits = 32)
WARNING:root:Could not interpret enumeratedValue '1': 'Rising edge trigger' in field 'IRQ_MD0' in register 'IRQ_MODE0_REG' (num_bits = 32)
WARNING:root:Could not interpret enumeratedValue '0': 'High-level trigger' in field 'IRQ_MD1' in register 'IRQ_MODE1_REG' (num_bits = 32)
WARNING:root:Could not interpret enumeratedValue '1': 'Rising edge trigger' in field 'IRQ_MD1' in register 'IRQ_MODE1_REG' (num_bits = 32)
WARNING:root:Could not interpret enumeratedValue '0': 'High-level trigger' in field 'IRQ_MD2' in register 'IRQ_MODE2_REG' (num_bits = 32)
WARNING:root:Could not interpret enumeratedValue '1': 'Rising edge trigger' in field 'IRQ_MD2' in register 'IRQ_MODE2_REG' (num_bits = 32)
WARNING:root:Could not interpret enumeratedValue '0': 'High-level trigger' in field 'IRQ_MD3' in register 'IRQ_MODE3_REG' (num_bits = 32)
WARNING:root:Could not interpret enumeratedValue '1': 'Rising edge trigger' in field 'IRQ_MD3' in register 'IRQ_MODE3_REG' (num_bits = 32)
WARNING:root:Could not interpret enumeratedValue '0': 'High-level trigger' in field 'IRQ_MD4' in register 'IRQ_MODE4_REG' (num_bits = 32)
WARNING:root:Could not interpret enumeratedValue '1': 'Rising edge trigger' in field 'IRQ_MD4' in register 'IRQ_MODE4_REG' (num_bits = 32)
INFO:root:'LEDC': Register block: None: {'LEDC_CTRL_REG': [0], 'LEDC_DATA_FINISH_CNT_REG': [8], 'LEDC_DATA_REG': [20], 'LEDC_DMA_CTRL_REG': [24], 'LEDC_INTERRUPT_CTRL_REG': [28], 'LEDC_INT_STS_REG': [32], 'LEDC_WAIT_TIME0_CTRL_REG': [16], 'LEDC_WAIT_TIME1_CTRL_REG': [40], 'LED_RESET_TIMING_CTRL_REG': [12], 'LED_T01_TIMING_CTRL_REG': [4]}
INFO:root:'LEDC': Register block: ('N', (0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31)): {'LEDC_FIFO_DATA_X': [48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92, 96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 148, 152, 156, 160, 164, 168, 172]}
WARNING:root:Offset is too complicated: 'Offset: 0x0050+N*0x0100+P*0x0004'
Traceback (most recent call last):
  File "/home/kassane/allwinner_extractor/phase3.py", line 1187, in infer_register_instance_structure
    register_offset = eval(spec[len("Offset:"):].strip(), eval_env)
  File "<string>", line 1, in <module>
NameError: name 'P' is not defined
Traceback (most recent call last):
  File "/home/kassane/allwinner_extractor/phase3.py", line 1462, in <module>
    process_register_block(global_registers, svd_registers)
  File "/home/kassane/allwinner_extractor/phase3.py", line 1313, in process_register_block
    common_vars_registers, simplified_offsets = infer_register_instance_structure(cluster_visible_registers, x_module_name)
  File "/home/kassane/allwinner_extractor/phase3.py", line 1187, in infer_register_instance_structure
    register_offset = eval(spec[len("Offset:"):].strip(), eval_env)
  File "<string>", line 1, in <module>
NameError: name 'P' is not defined
make: *** [Makefile:16: phase3_host.svd] Error 1

Please try current master--it should be working without any workarounds now.

ove  from  the  USBSUSPEND  state  to  the  USBRESUME  state  after  detecting  the  resume  signaling  from  a  downstream port.  HC enters USBSUSPEND after a software reset, whereas it enters  USBRESET after a hardware reset. The latter also resets the Root  Hub and asserts subsequent reset signaling to downstream ports. '] was not understood
WARNING:root:'HcRevision': Field names are not all known; for example the one described by: 'BulkListEnable  This bit is set to enable the processing of the Bulk list in the next  Frame. If cleared by HCD, the processing of the Bulk list does not  occur  after  the  next  SOF.  HC  checks  this  bit  whenever  it  determines to process the list. When disabled, HCD may modify  the  list.  If  is  pointing  to  an  ED  to  be  removed,  HCD  must  advance  the  pointer  by  updating    before re-enabling processing of the list. '
WARNING:root:'HcRevision': Field names are not all known; for example the one described by: 'ControlListEnable  This bit is set to enable the processing of the Control list in the next  Frame. If cleared by HCD, the processing of the Control list does  not occur after the next SOF. HC must check this bit whenever it  determines to process the list. When disabled, HCD may modify  the list. If  is pointing to an ED to be removed,  HCD  must  advance  the  pointer  by  updating  before re-enabling processing of the list. '
WARNING:root:'HcRevision': Field names are not all known; for example the one described by: 'PeriodicListEnable    This bit is set to enable the processing of periodic list in the next  Frame. If cleared by HCD, processing of the periodic list does not  occur  after  the  next  SOF.  HC  must  check  this  bit  before  it  starts  processing the list. '
INFO:root:'HcRevision': Guessed field name 'HC_SUPPORTS_REMOTE_WAKEUP_SIGNALING'
WARNING:root:'HcRhPortStatus': Default 'PortResetStatusChange' for field ['20', 'R/W ', 'R/W  0x0 ', 'PortResetStatusChange', 'This bit is set at the end of the 10-ms port reset signal. The HCD  writes a ‘1’ to clear this bit. Writing a ‘0’ has no effect.  0  port reset is not complete  1  port reset is complete '] was not understood
WARNING:root:'HcRhPortStatus': Default 'PortResetStatusChange' for field ['20', 'R/W ', 'R/W  0x0 ', 'PortResetStatusChange', 'This bit is set at the end of the 10-ms port reset signal. The HCD  writes a ‘1’ to clear this bit. Writing a ‘0’ has no effect.  0  port reset is not complete  1  port reset is complete '] was not understood
WARNING:root:'HcRhPortStatus': Default 'PortResetStatusChange' for field ['20', 'R/W ', 'R/W  0x0 ', 'PortResetStatusChange', 'This bit is set at the end of the 10-ms port reset signal. The HCD  writes a ‘1’ to clear this bit. Writing a ‘0’ has no effect.  0  port reset is not complete  1  port reset is complete '] was not understood
WARNING:root:'HcRhPortStatus': Default 'PortResetStatusChange' for field ['20', 'R/W ', 'R/W  0x0 ', 'PortResetStatusChange', 'This bit is set at the end of the 10-ms port reset signal. The HCD  writes a ‘1’ to clear this bit. Writing a ‘0’ has no effect.  0  port reset is not complete  1  port reset is complete '] was not understood
WARNING:root:'HcRhPortStatus': Default 'PortResetStatusChange' for field ['20', 'R/W ', 'R/W  0x0 ', 'PortResetStatusChange', 'This bit is set at the end of the 10-ms port reset signal. The HCD  writes a ‘1’ to clear this bit. Writing a ‘0’ has no effect.  0  port reset is not complete  1  port reset is complete '] was not understood
WARNING:root:'HcRhPortStatus': Default 'PortResetStatusChange' for field ['20', 'R/W ', 'R/W  0x0 ', 'PortResetStatusChange', 'This bit is set at the end of the 10-ms port reset signal. The HCD  writes a ‘1’ to clear this bit. Writing a ‘0’ has no effect.  0  port reset is not complete  1  port reset is complete '] was not understood
WARNING:root:'HcRhPortStatus': Field names are not all known; for example the one described by: 'This bit is set at the end of the 10-ms port reset signal. The HCD  writes a ‘1’ to clear this bit. Writing a ‘0’ has no effect.  0  port reset is not complete  1  port reset is complete '
WARNING:root:'HcRhPortStatus': Default 'PortOverCurrentIndicatorChange' for field ['19', 'R/W ', 'R/W  0x0 ', 'PortOverCurrentIndicatorChange ', 'This bit is valid only if overcurrent conditions are reported on a  per-port  basis.  This  bit  is  set  when  Root  Hub  changes  the  PortOverCurrentIndicator  bit.  The HCD writes  a  ‘1’  to  clear  this  bit. Writing a ‘0’ has no effect.  0  no change in  PortOverCurrentIndicator   1  PortOverCurrentIndicator  has changed '] was not understood
WARNING:root:'HcRhPortStatus': Field names are not all known; for example the one described by: 'This bit is valid only if overcurrent conditions are reported on a  per-port  basis.  This  bit  is  set  when  Root  Hub  changes  the  PortOverCurrentIndicator  bit.  The HCD writes  a  ‘1’  to  clear  this  bit. Writing a ‘0’ has no effect.  0  no change in  PortOverCurrentIndicator   1  PortOverCurrentIndicator  has changed '
WARNING:root:'HcRhPortStatus': Default 'PortSuspendStatusChange' for field ['18', 'R/W ', 'R/W  0x0 ', 'PortSuspendStatusChange ', 'This bit is set when the full resume sequence has been completed.  This sequence includes the 20-s resume pulse, LS EOP, and 3-ms  resychronization  delay.  The  HCD  writes  a  ‘1’  to  clear  this  bit.  Writing  a  ‘0’  has  no  effect.  This  bit  is  also  cleared  when  ResetStatusChange  is set.  0  resume is not completed  1  resume completed '] was not understood
WARNING:root:'HcRhPortStatus': Default 'PortEnableStatusChange' for field ['17', 'R/W ', 'R/W  0x0 ', 'PortEnableStatusChange ', 'This bit is set when hardware events cause the  PortEnableStatus  bit to be cleared. Changes from HCD writes do not set this bit. The  HCD writes a ‘1’ to clear this bit. Writing a ‘0’ has no effect. 0  no change in  PortEnableStatus   1  change in  PortEnableStatus  '] was not understood
WARNING:root:'HcRhPortStatus': Default 'ConnectStatusChange' for field ['16', 'R/W ', 'R/W  0x0 ', 'ConnectStatusChange ', 'This bit is set whenever a connect or disconnect event occurs. The  HCD  writes  a  ‘1’  to  clear  this  bit.  Writing  a  ‘0’  has  no  effect.  If  CurrentConnectStatus  is  cleared  when  a  SetPortReset,SetPortEnable ,  or  SetPortSuspend  write  occurs,  this  bit  is  set  to force  the  driver  to  re-evaluate  the  connection  status  since  these writes  should  not  occur  if  the  port  is  disconnected.  0  no change in  PortEnableStatus   1  change in  PortEnableStatus     Note: If the DeviceRemovable[NDP] bit is set, this bit is set only  after a Root Hub reset to inform the system that the device is  attached.  '] was not understood
WARNING:root:'HcRhPortStatus': Field name could not be determined: ['8', 'R/W ', 'R/W  0x1 ', '(read)', 'PortPowerStatus  This bit reflects the port’s power status, regardless of the type of  power switching implemented. This bit is cleared if an overcurrent  condition is detected. HCD sets this bit by writing  SetPortPower   or  SetGlobalPower . HCD clears this bit by writing  ClearPortPower  or  ClearGlobalPower . Which power control switches are enabled  is  determined  by  PowerSwitchingMode   and  PortPortControlMask[ NumberDownstreamPort ] .  In  global  switching  mode( PowerSwitchingMode =0),  only  Set/ClearGlobalPower  controls  this bit. In per-port power switching ( PowerSwitchingMode =1), if  the  PortPowerControlMask[NDP]  bit  for  the  port  is  set,  only  Set/ClearPortPower  commands  are  enabled.  If  the  mask  is  not  set,  only  Set/ClearGlobalPower  commands  are  enabled.  When  port power is disabled,  CurrentConnectStatus ,  PortEnableStatus ,  PortSuspendStatus , and  PortResetStatus  should be reset.  0  port power is off  1  port power is on    (write) SetPortPower   The HCD writes a ‘1’ to set the  PortPowerStatus  bit. Writing a ‘0’  has no effect.    Note:  This  bit  is  always  reads  ‘1b’  if  power  switching  is  not  supported. '] (tried: '')
WARNING:root:'HcRhPortStatus': Field names are not all known; for example the one described by: 'PortEnableStatus  This  bit  indicates  whether  the  port  is  enabled  or  disabled.  The  Root  Hub  may  clear  this  bit  when  an  overcurrent  condition,  disconnect  event,  switched-off  power,  or  operational  bus  error  such  as  babble  is  detected.  This  change  also  causes  PortEnabledStatusChange  to be set. HCD sets this bit by writing  SetPortEnable  and  clears  it  by  writing  ClearPortEnable .  This  bit  cannot be set when  CurrentConnectStatus  is cleared. This bit is  also  set,  if  not  already,  at  the  completion  of  a  port  reset  when  ResetStatusChange  is set or port suspend when  SuspendStatusChange  is set.  0  port is disabled  1  port is enabled    (write) SetPortEnable  The HCD sets  PortEnableStatus  by writing a ‘1’. Writing a ‘0’ has  no effect. If  CurrentConnectStatus  is cleared, this write does not  set  PortEnableStatus ,  but  instead  sets  ConnectStatusChange .  This informs the driver that it attempted to enable a disconnected  Port. '
INFO:root:'HcRhPortStatus': Guessed field name 'FULL_RESUME_SEQUENCE_HAS_BEEN_COMPLETED'
INFO:root:'HcRhPortStatus': Guessed field name 'HARDWARE_EVENTS_CAUSE_THE_PORTENABLESTATUS_BIT'
INFO:root:'HcRhPortStatus': Guessed field name 'WHENEVER_A_CONNECT_OR_DISCONNECT_EVENT'
WARNING:root:'HcRhStatus_Register': Field names are not all known; for example the one described by: 'OverCurrentIndicatorChang  This  bit  is  set  by  hardware  when  a  change  has  occurred  to  the  OverCurrentIndicator  field of this register. The HCD clears this bit  by writing a ‘1’. Writing a ‘0’ has no effect.'
WARNING:root:'HcRhStatus_Register': Default 'OverCurrentIndicator' for field ['1', 'R ', 'R/W  0x0 ', 'OverCurrentIndicator ', 'This bit reports overcurrent conditions when the global reporting  is implemented. When set, an overcurrent condition exists. When  cleared, all power operations are normal.    If  per-port  overcurrent  protection  is  implemented  this  bit  is  always ‘0’ '] was not understood
INFO:root:'HcRhStatus_Register': Guessed field name 'REPORTS_OVERCURRENT_CONDITIONS_WHEN_THE_GLOBAL'
WARNING:root:'PHY_CTRL': Field names are not all known; for example the one described by: 'bist_en_a '
WARNING:root:'PORTSC': Field names are not all known; for example the one described by: 'Line Status  These bits reflect the current logical levels of the D+ (bit11) and D- (bit10) signal lines. These bits are used for detection of low-speed  USB  devices  prior  to  port  reset  and  enable  sequence.  This  read  only  field  is  valid  only  when  the  port  enable  bit  is  zero  and  the  current connect status bit is set to a one.  The encoding of the bits are:  Bit[11:10]  USB State  Interpretation  00b  SE0  Not Low-speed device, perform EHCI  reset.  10b  J-state  Not Low-speed device, perform EHCI  reset.  01b  K-state  Low-speed  device,  release  ownership of port.  11b  Undefined  Not Low-speed device, perform EHCI  reset.  This value of this field is undefined if Port Power is zero. '
WARNING:root:'USBCMD': Field names are not all known; for example the one described by: 'Frame List Size  This  field  is  R/W  only  if  Programmable  Frame  List  Flag  in  the  HCCPARAMS registers is set to a one. This field specifies the size of  the    Frame list. The size the frame list controls which bits in the Frame  Index    Register should be used for the Frame List Current index. Values  mean:  Bits  Meaning  00b  1024 elements(4096bytes)Default value  01b  512 elements(2048byts)  10b  256  elements(1024bytes)For  resource-constrained  condition  11b  reserved  The default value is ‘00b’. '
WARNING:root:'USBINTR': Field names are not all known; for example the one described by: 'Interrupt on Async Advance Enable  When this bit is 1, and the Interrupt on Async Advance bit in the  USBSTS register is 1, the host controller will issue an interrupt at  the  next  interrupt  threshold.  The  interrupt  is  acknowledged  by  software clearing the Interrupt on Async Advance bit. '
WARNING:root:'USBINTR': Field names are not unique: ['HOST_SYSTEM_ERROR_ENABLE_WHEN_THIS', 'FRAME_LIST_ROLLOVER_ENABLE_WHEN_THIS', 'PORT_CHANGE_INTERRUPT_ENABLE_WHEN_THIS', 'USB', 'USB']
WARNING:root:'USBSTS': Field names are not unique: ['ASYNCHRONOUS_SCHEDULE_STATUS_THE_BIT_REPORTS', 'PERIODIC_SCHEDULE_STATUS_THE_BIT_REPORTS', 'RECLAMATION_THIS_IS_A_READ-ONLY_STATUS', 'HC', 'INTERRUPT_ON_ASYNC_ADVANCE_SYSTEM_SOFTWARE', 'HOST_SYSTEM_ERROR_THE_HOST_CONTROLLER', 'FRAME_LIST_ROLLOVER_THE_HOST_CONTROLLER', 'PORT_CHANGE_DETECT_THE_HOST_CONTROLLER', 'USB', 'USB']
WARNING:root:'USB_CTRL': Field name could not be determined: ['18', 'R/W ', '0 ', '1: Within 2 us of the resume-K to SE0 transition \n0: Random time value of the resume-K to SE0 transition '] (tried: '')
WARNING:root:'USB_CTRL': Field names are not unique: ['DMA', 'OHCI', 'PP2VBUS', 'AHB', 'AHB', 'AHB', 'AHB', 'ULPI']
WARNING:root:'USBCMD': field 'ASYNCHRONOUS_SCHEDULE_PARK_MODE_ENABLE': Maybe parse error; description='Asynchronous Schedule Park Mode Enable (OPTIONAL)  If the Asynchronous Park Capability bit in the HCCPARAMS register  is a one, then this bit defaults to a 1 and is R/W. Otherwise the bit  must be a zero and is Read Only. Software uses this bit to enable  or disable Park mode. When this bit is one, Park mode is enabled.  When this bit is zero, Park mode is disabled. '
WARNING:root:register 'USB_SPDCR' field 'PORT' enum variants are not unique ([['00', ' Port Disable when no-se0 detect before SOF '], ['01', ' Port Disable when no-se0 detect before SOF '], ['10', ' No Port Disable when no-se0 detect before SOF '], ['11', ' Port Disable when no-se0 3 time detect before SOF during 8    frames     ']], counter = 8). Giving up.
WARNING:root:[['USB1 ', '0x04200000   ']]: Removing cluster 'OHCI CONTROL AND STATUS PARTITION REGISTER' since it's empty
WARNING:root:[['USB1 ', '0x04200000   ']]: Removing cluster 'OHCI MEMORY POINTER PARTITION REGISTER' since it's empty
WARNING:root:[['USB1 ', '0x04200000   ']]: Removing cluster 'OHCI FRAME COUNTER PARTITION REGISTER' since it's empty
WARNING:root:[['USB1 ', '0x04200000   ']]: Removing cluster 'EHCI CAPABILITY REGISTER' since it's empty
WARNING:root:[['USB1 ', '0x04200000   ']]: Removing cluster 'OHCI ROOT HUB PARTITION REGISTER' since it's empty
WARNING:root:[['USB1 ', '0x04200000   ']]: Removing cluster 'EHCI OPERATIONAL REGISTER' since it's empty
WARNING:root:'TMR0_INTV_VALUE_REG': Invalid field ['Take the system clock and timer clock source into consideration when setting the interval value.', '', '', '']: Bitrange error
WARNING:root:'TMR1_INTV_VALUE_REG': Invalid field ['Take the system clock and timer clock source into consideration when setting the interval value.', '', '', '']: Bitrange error
WARNING:root:Could not interpret enumeratedValue 'Others': 'Reserved  Note: The corresponding clock cycles for the interval value (IV)  depends on the frequency of the clock: Cycles = F  * IV.  For example, to get a interval value of 0.5 second, if the clock  source  is  HOSC_32K  (whose  frequency  is  32  KHz),  the  cycle  number  is  16,000;  if  the  clock  source  is  LOSC_32K  (whose  frequency is 32.768 kHz), the cycle number is 16,384.' in field 'WDOG_INTV_VALUE' in register 'WDOG_MODE_REG' (num_bits = 4)
INFO:root:'PWM': Register block: None: {'CER': [192], 'CIER': [16], 'CISR': [20], 'PCCR01': [32], 'PCCR23': [36], 'PCCR45': [40], 'PCCR67': [44], 'PCGR': [64], 'PDZCR01': [96], 'PDZCR23': [100], 'PDZCR45': [104], 'PDZCR67': [108], 'PER': [128], 'PGR0': [144], 'PGR1': [148], 'PGR2': [152], 'PGR3': [156], 'PIER': [0], 'PISR': [4]}
INFO:root:'PWM': Register block: (('N', (0, 1, 2, 3, 4, 5, 6, 7)),): {'CCR': [272, 304, 336, 368, 400, 432, 464, 496], 'CFLR': [280, 312, 344, 376, 408, 440, 472, 504], 'CRLR': [276, 308, 340, 372, 404, 436, 468, 500], 'PCNTR': [264, 296, 328, 360, 392, 424, 456, 488], 'PPR': [260, 292, 324, 356, 388, 420, 452, 484]}
WARNING:root:Could not interpret enumeratedValue '0': '1 cycle' in field 'PWM_ENTIRE_CYCLE' in register 'PPR' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1': '2 cycles  …  N: N+1 cycles  If the register needs to be modified dynamically, the PCLK should  be faster than the PWM CLK.' in field 'PWM_ENTIRE_CYCLE' in register 'PPR' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0': '0 cycle' in field 'PWM_ACT_CYCLE' in register 'PPR' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1': '1 cycle  …  N: N cycles' in field 'PWM_ACT_CYCLE' in register 'PPR' (num_bits = 16)
WARNING:root:'CSIC_DMA_CFG_REG': Field names are not unique: ['PAD_VAL', 'YUV', 'YUV', 'OUTPUT_FMT', 'VFLIP_EN', 'HFLIP_EN', 'FIELD_SEL', 'FPS_DS', 'MIN_SDR_WR_SIZE']
WARNING:root:'PRS_CH3_LINE_TIME_REG': Invalid field ['31:16  RO', '0x0 ', 'PRS_CH3_HBLK_TIME ', 'Time of H Blanking when vsync is valid  The unit is csi_top_clk cycle ']: Bitrange error
WARNING:root:'PRS_NCSI_IF_CFG_REG': Field names are not all known; for example the one described by: 'Source type  Bit 20–23 corresponding to the SRC_TYPEs for channel0–3 \n0: Progressed \n1: Interlaced '
WARNING:root:'PRS_NCSI_IF_CFG_REG': Field names are not all known; for example the one described by: 'YUV (separate syncs): \n00000:  RAW  or  YUV420/YUYV422  (each  cycle  one  component  input)  Others: Reserved      CCIR656 (embedded syncs): \n00100: BT656 1 channel \n01100: BT656 2 channels (All data interleaved in one data bus) \n01110: BT656 4 channels (All data interleaved in one data bus)  Others: Reserved   '
WARNING:root:Could not interpret enumeratedValue '0': 'Unmask' in field 'BIST_DATA_MASK' in register 'CSIC_BIST_DATA_MASK_REG' (num_bits = 32)
WARNING:root:Could not interpret enumeratedValue '1': 'Mask' in field 'BIST_DATA_MASK' in register 'CSIC_BIST_DATA_MASK_REG' (num_bits = 32)
WARNING:root:Could not interpret enumeratedValue '0': 'low' in field 'DATA_STA' in register 'CSIC_PRS_SIGNAL_STA_REG' (num_bits = 24)
WARNING:root:Could not interpret enumeratedValue '1': 'high' in field 'DATA_STA' in register 'CSIC_PRS_SIGNAL_STA_REG' (num_bits = 24)
WARNING:root:Could not interpret enumeratedValue '0': 'no down sample' in field 'CH3_FPS_DS' in register 'PRS_CAP_REG' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue '1': '1/2 fps, only receives the first frame every 2 frames' in field 'CH3_FPS_DS' in register 'PRS_CAP_REG' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue '0': 'no down sample' in field 'CH2_FPS_DS' in register 'PRS_CAP_REG' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue '1': '1/2 fps, only receives the first frame every 2 frames' in field 'CH2_FPS_DS' in register 'PRS_CAP_REG' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue '0': 'no down sample' in field 'CH1_FPS_DS' in register 'PRS_CAP_REG' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue '1': '1/2 fps, only receives the first frame every 2 frames' in field 'CH1_FPS_DS' in register 'PRS_CAP_REG' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue '0': 'no down sample' in field 'CH0_FPS_DS' in register 'PRS_CAP_REG' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue '1': '1/2 fps, only receives the first frame every 2 frames' in field 'CH0_FPS_DS' in register 'PRS_CAP_REG' (num_bits = 4)
WARNING:root:register 'CSIC_DMA_CFG_REG' field 'OUTPUT_FMT' enum variants are not unique ([['0000', ' field-raw-8 '], ['0001', ' field-raw-10 '], ['0010', ' field-raw-12 '], ['0011', ' reserved '], ['0100', ' field-rgb565 '], ['0101', ' field-rgb888 '], ['0110', ' field-prgb888 '], ['0111', ' reserved '], ['1000', ' frame-raw-8 '], ['1001', ' frame-raw-10 '], ['1010', ' frame-raw-12 '], ['1011', ' reserved '], ['1100', ' frame-rgb565 '], ['1101', ' frame-rgb888 '], ['1110', ' frame-prgb888 '], ['1111', ' reserved    When the input format is set to YUV422 '], ['0000', ' field planar YCbCr 422 '], ['0001', ' field planar YCbCr 420 '], ['0010', ' frame planar YCbCr 420 '], ['0011', ' frame planar YCbCr 422 '], ['0100', ' field planar YCbCr 422 UV combined (UV sequence) '], ['0101', ' field planar YCbCr 420 UV combined (UV sequence) '], ['0110', ' frame planar YCbCr 420 UV combined (UV sequence) '], ['0111', ' frame planar YCbCr 422 UV combined (UV sequence) '], ['1000', ' filed planar YCbCr 422 UV combined (VU sequence) '], ['1001', ' field planar YCbCr 420 UV combined (VU sequence) '], ['1010', ' frame planar YCbCr 420 UV combined (VU sequence) '], ['1011', ' frame planar YCbCr 422 UV combined (VU sequence) '], ['1100', ' reserved '], ['1101', ' field YCbCr 400   '], ['1110', ' reserved '], ['1111', ' frame YCbCr 400      When the input format is set to YUV420 '], ['0000', ' reserved '], ['0001', ' field planar YCbCr 420 '], ['0010', ' frame planar YCbCr 420 '], ['0011', ' reserved '], ['0100', ' reserved '], ['0101', ' field planar YCbCr 420 UV combined (UV sequence) '], ['0110', ' frame planar YCbCr 420 UV combined (UV sequence)  0111~1000: reserved '], ['1001', ' field planar YCbCr 420 UV combined (VU sequence) '], ['1010', ' frame planar YCbCr 420 UV combined (VU sequence)  1011~1100: reserved '], ['1101', ' field YCbCr 400   '], ['1110', ' reserved '], ['1111', ' frame YCbCr 400 ']], counter = 2). Giving up.
WARNING:root:Could not interpret enumeratedValue '0': 'no down sample' in field 'FPS_DS' in register 'CSIC_DMA_CFG_REG' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue '1': '1/2 fps, only receives the first frame every 2 frames' in field 'FPS_DS' in register 'CSIC_DMA_CFG_REG' (num_bits = 4)
WARNING:root:register 'CSIC_DMA_CFG_REG' field 'OUTPUT_FMT' enum variants are not unique ([['0000', ' field-raw-8 '], ['0001', ' field-raw-10 '], ['0010', ' field-raw-12 '], ['0011', ' reserved '], ['0100', ' field-rgb565 '], ['0101', ' field-rgb888 '], ['0110', ' field-prgb888 '], ['0111', ' reserved '], ['1000', ' frame-raw-8 '], ['1001', ' frame-raw-10 '], ['1010', ' frame-raw-12 '], ['1011', ' reserved '], ['1100', ' frame-rgb565 '], ['1101', ' frame-rgb888 '], ['1110', ' frame-prgb888 '], ['1111', ' reserved    When the input format is set to YUV422 '], ['0000', ' field planar YCbCr 422 '], ['0001', ' field planar YCbCr 420 '], ['0010', ' frame planar YCbCr 420 '], ['0011', ' frame planar YCbCr 422 '], ['0100', ' field planar YCbCr 422 UV combined (UV sequence) '], ['0101', ' field planar YCbCr 420 UV combined (UV sequence) '], ['0110', ' frame planar YCbCr 420 UV combined (UV sequence) '], ['0111', ' frame planar YCbCr 422 UV combined (UV sequence) '], ['1000', ' filed planar YCbCr 422 UV combined (VU sequence) '], ['1001', ' field planar YCbCr 420 UV combined (VU sequence) '], ['1010', ' frame planar YCbCr 420 UV combined (VU sequence) '], ['1011', ' frame planar YCbCr 422 UV combined (VU sequence) '], ['1100', ' reserved '], ['1101', ' field YCbCr 400   '], ['1110', ' reserved '], ['1111', ' frame YCbCr 400      When the input format is set to YUV420 '], ['0000', ' reserved '], ['0001', ' field planar YCbCr 420 '], ['0010', ' frame planar YCbCr 420 '], ['0011', ' reserved '], ['0100', ' reserved '], ['0101', ' field planar YCbCr 420 UV combined (UV sequence) '], ['0110', ' frame planar YCbCr 420 UV combined (UV sequence)  0111~1000: reserved '], ['1001', ' field planar YCbCr 420 UV combined (VU sequence) '], ['1010', ' frame planar YCbCr 420 UV combined (VU sequence)  1011~1100: reserved '], ['1101', ' field YCbCr 400   '], ['1110', ' reserved '], ['1111', ' frame YCbCr 400 ']], counter = 2). Giving up.
WARNING:root:Could not interpret enumeratedValue '0': 'no down sample' in field 'FPS_DS' in register 'CSIC_DMA_CFG_REG' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue '1': '1/2 fps, only receives the first frame every 2 frames' in field 'FPS_DS' in register 'CSIC_DMA_CFG_REG' (num_bits = 4)
WARNING:root:[['CSIC_CCU ', '0x05800000 '], ['CSIC_TOP ', '0x05800800 '], ['CSIC_PARSER0 ', '0x05801000 '], ['CSIC_DMA0 ', '0x05809000 '], ['CSIC_DMA1 ', '0x05809200   ']]: Registers not used in any peripheral: ['CSIC_BIST_CTRL_REG', 'CSIC_BIST_END_ADDR_REG', 'CSIC_BIST_START_ADDR_REG', 'CSIC_DMA_F2_BUFA_RESULT_REG', 'PRS_CH0_INFMT_REG', 'PRS_CH0_INPUT_PARA0_REG', 'PRS_CH0_INPUT_PARA1_REG', 'PRS_CH0_INPUT_PARA2_REG', 'PRS_CH0_INPUT_PARA3_REG', 'PRS_CH0_INT_EN_REG', 'PRS_CH0_INT_STA_REG', 'PRS_CH0_OUTPUT_HSIZE_REG', 'PRS_CH0_OUTPUT_VSIZE_REG', 'PRS_CH1_INFMT_REG', 'PRS_CH1_INPUT_PARA0_REG', 'PRS_CH1_INPUT_PARA1_REG', 'PRS_CH1_INPUT_PARA2_REG', 'PRS_CH1_INPUT_PARA3_REG', 'PRS_CH1_INT_EN_REG', 'PRS_CH1_INT_STA_REG', 'PRS_CH1_OUTPUT_HSIZE_REG', 'PRS_CH1_OUTPUT_VSIZE_REG', 'PRS_CH2_INFMT_REG', 'PRS_CH2_INPUT_PARA0_REG', 'PRS_CH2_INPUT_PARA1_REG', 'PRS_CH2_INPUT_PARA2_REG', 'PRS_CH2_INPUT_PARA3_REG', 'PRS_CH2_INT_EN_REG', 'PRS_CH2_INT_STA_REG', 'PRS_CH2_OUTPUT_HSIZE_REG', 'PRS_CH2_OUTPUT_VSIZE_REG', 'PRS_CH3_INFMT_REG', 'PRS_CH3_INPUT_PARA0_REG', 'PRS_CH3_INPUT_PARA1_REG', 'PRS_CH3_INPUT_PARA2_REG', 'PRS_CH3_INPUT_PARA3_REG', 'PRS_CH3_INT_EN_REG', 'PRS_CH3_INT_STA_REG', 'PRS_CH3_OUTPUT_HSIZE_REG', 'PRS_CH3_OUTPUT_VSIZE_REG', 'PRS_NCSI_IF_CFG_REG']
WARNING:root:'CE_TPR': Invalid field ['Before performing the burning operation, ensure that the power supply of the eFuse power pin is stable.', '', '', '']: Bitrange error
WARNING:root:'CE_TPR': Invalid field ['After the burning operation is completed, cancel the power supply of the eFuse power pin.', 'The following table contains acronyms and abbreviations used in this document. ', '', '']: Bitrange error
WARNING:root:Could not interpret enumeratedValue 'xxx1': 'Algorithm not support' in field 'TASK_CHANNEL3' in register 'CE_ESR' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue 'xx1x': 'Data length error' in field 'TASK_CHANNEL3' in register 'CE_ESR' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue 'x1xx': 'keysram access error for AES' in field 'TASK_CHANNEL3' in register 'CE_ESR' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue 'xxx1': 'Algorithm not support' in field 'TASK_CHANNEL2' in register 'CE_ESR' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue 'xx1x': 'Data length error' in field 'TASK_CHANNEL2' in register 'CE_ESR' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue 'x1xx': 'keysram access error for AES' in field 'TASK_CHANNEL2' in register 'CE_ESR' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue 'xxx1': 'Algorithm not support' in field 'TASK_CHANNEL1' in register 'CE_ESR' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue 'xx1x': 'Data length error' in field 'TASK_CHANNEL1' in register 'CE_ESR' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue 'x1xx': 'keysram access error for AES' in field 'TASK_CHANNEL1' in register 'CE_ESR' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue 'xxx1': 'Algorithm not support' in field 'TASK_CHANNEL0' in register 'CE_ESR' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue 'xx1x': 'Data length error' in field 'TASK_CHANNEL0' in register 'CE_ESR' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue 'x1xx': 'keysram access error for AES' in field 'TASK_CHANNEL0' in register 'CE_ESR' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue '0': 'Disable' in field 'TASK' in register 'CE_ICR' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue '1': 'Enable' in field 'TASK' in register 'CE_ICR' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue '0': 'Not finished' in field 'TASK' in register 'CE_ISR' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue '1': 'Finished  It indicates whether task is completed.    Write the corresponding channel bit of the register to clear the  end flag.  When the last task in the task chain ends, the operation of the  task chain will end normally. If the task fails in the middle, the  task  chain  will  be  aborted.  The  CE_ISR  register  will  be  automatically  updated  when  it  ends  normally  or  aborts  abnormally.  And  it  is  determined  whether  to  generate  an  interrupt  signal  according  to  the  IE  configuration  (bit31)  of   when the current task ends or aborts.  If  using  interrupt,  after  receiving  the  interrupt,  read  the  corresponding  channel  bit  of  CE_ISR  to  judge  whether  it  ends  successfully or stops failure.  If  not  using  interrupt,  the  CE_ISR  status  register  can  be  continuously queried for the channel bit until the successful end  flag is set or the failure stop flag is set. Write the corresponding  channel bit of the register to clear the end flag.  If  it  fails  to  stop,  you  can  read  the  error  code  on  the  channel  corresponding to the   register.' in field 'TASK' in register 'CE_ISR' (num_bits = 4)
WARNING:root:register 'CIR_RXCFG' field 'NTHR' enum variants are not unique ([['0', ' All samples are recorded into RX FIFO '], ['1', ' If the signal is only one sample duration, it is taken as noise  and discarded. '], ['2', ' If the signal is less than (<=) two sample duration, it is taken  as noise and discarded.  … '], ['61', ' If the signal is less than (<=) sixty-one sample duration, it is  taken as noise and discarded. ']], counter = 8). Giving up.
WARNING:root:Could not interpret enumeratedValue '0': 'No available data in RX FIFO' in field 'RAC' in register 'CIR_RXSTA' (num_bits = 7)
WARNING:root:Could not interpret enumeratedValue '1': '1-byte available data in RX FIFO' in field 'RAC' in register 'CIR_RXSTA' (num_bits = 7)
WARNING:root:register 'CIR_TXINT' field 'TPEI_EN' enum variants are not unique ([['0', ' Disable '], ['1', ' Enable    TUI_EN  Transmitter  FIFO  Underrun  Interrupt  Enable  for  Non-cyclical  Pulse '], ['0', ' Disable '], ['1', ' Enable   ']], counter = 2). Giving up.
WARNING:root:register 'CIR_TXSTA' field 'TPE' enum variants are not unique ([['0', '  Transmissions  of  address,  control  and  data  fields  not  completed '], ['1', ' Transmissions of address, control and data fields completed    TUR  Transmitter FIFO Underrun Flag for Non-cyclical Pulse '], ['0', ' No transmitter FIFO underrun '], ['1', ' Transmitter FIFO underrun  Writing 1 clears this bit.   ']], counter = 5). Giving up.
WARNING:root:'SPI_NDMA_MODE_CTL': Default 17 for field ['7:6', 'R/W ', '0x11 ', 'SPI_ACT_M  SPI NDMA Active Mode \n00: dma_active is low   \n01: dma_active is high \n10: dma_active is controlled by dma_request (DRQ) \n11: dma_active is controlled by controller '] does not fit into slot with bitrange 7:6
WARNING:root:register 'DBI_CTL_0' field 'RGB_SOURCE_FORMAT' enum variants are not unique ([('0000', ' RGB '), ('0001', ' RBG '), ('0010', ' GRB '), ('0011', ' GBR '), ('0100', ' BRG '), ('0101', ' BGR'), ('Others', ' Reserved    When video_source_type is RGB16 (DBI_CTL_0[bit0] = 1) '), ('0000', ' RGB  0001~0100: Reserved '), ('0101', ' BGR '), ('0110', ' GRBG_0 {G[5:3]R[4:0]B[4:0]G[2:0]} '), ('0111', ' GBRG_0 {G[5:3]B[4:0]R[4:0]G[2:0]} '), ('1000', ' GRBG_1 {G[2:0]R[4:0]B[4:0]G[5:3]} '), ('1001', ' GBRG_1 {G[2:0]B[4:0]R[4:0]G[5:3]}  Others: Reserved ')], counter = 2). Giving up.
WARNING:root:register 'DBI_CTL_1' field 'RGB666_FMT' enum variants are not unique ([['00', ' Normal Format '], ['01', ' Special Format for ILITEK '], ['10', ' Special Format for New Vision ']], counter = 3). Giving up.
WARNING:root:Could not interpret enumeratedValue '0': '0 burst' in field 'DBC' in register 'SPI_BCC' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue '1': '1 burst  …  N: N bursts  Cannot be written when XCH=1' in field 'DBC' in register 'SPI_BCC' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue '0': '0 burst' in field 'STC' in register 'SPI_BCC' (num_bits = 24)
WARNING:root:Could not interpret enumeratedValue '1': '1 burst  …  N: N bursts  Cannot be written when XCH=1' in field 'STC' in register 'SPI_BCC' (num_bits = 24)
WARNING:root:Could not interpret enumeratedValue '0': '0 byte in TXFIFO' in field 'TF_CNT' in register 'SPI_FSR' (num_bits = 8)
WARNING:root:Could not interpret enumeratedValue '1': '1 byte in TXFIFO  …' in field 'TF_CNT' in register 'SPI_FSR' (num_bits = 8)
WARNING:root:Could not interpret enumeratedValue '0': '0 byte in RXFIFO' in field 'RF_CNT' in register 'SPI_FSR' (num_bits = 8)
WARNING:root:Could not interpret enumeratedValue '1': '1 byte in RXFIFO  …' in field 'RF_CNT' in register 'SPI_FSR' (num_bits = 8)
WARNING:root:Could not interpret enumeratedValue '0': '0 burst' in field 'MBC' in register 'SPI_MBC' (num_bits = 24)
WARNING:root:Could not interpret enumeratedValue '1': '1 burst  …  N: N bursts  Cannot be written when XCH=1.' in field 'MBC' in register 'SPI_MBC' (num_bits = 24)
WARNING:root:Could not interpret enumeratedValue '0': '0 burst' in field 'MWTC' in register 'SPI_MTC' (num_bits = 24)
WARNING:root:Could not interpret enumeratedValue '1': '1 burst  …  N: N bursts  Cannot be written when XCH=1.' in field 'MWTC' in register 'SPI_MTC' (num_bits = 24)
WARNING:root:register 'SPI_NDMA_MODE_CTL' field 'SPI_ACT_M' enum variants are not unique ([['00', ' dma_active is low   '], ['01', ' dma_active is high '], ['10', ' dma_active is controlled by dma_request (DRQ) '], ['11', ' dma_active is controlled by controller ']], counter = 4). Giving up.
WARNING:root:Could not interpret enumeratedValue '0': 'No wait states inserted  n: n SPI_SCLK wait states inserted  Cannot be written when XCH=1.' in field 'SWC' in register 'SPI_WCR' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue '0': 'No wait states inserted  n: n SPI_SCLK wait states inserted  Cannot be written when XCH=1.' in field 'WCC' in register 'SPI_WCR' (num_bits = 16)
WARNING:root:'DMAC_AUTO_GATE_REG': Invalid field ['When initializing the DMA Controller, the bit[2] should be set up.', '', '', '']: Bitrange error
INFO:root:'DMAC': Register block: None: {'DMAC_AUTO_GATE_REG': [40], 'DMAC_IRQ_EN_REG0': [0], 'DMAC_IRQ_EN_REG1': [4], 'DMAC_IRQ_PEND_REG0': [16], 'DMAC_IRQ_PEND_REG1': [20], 'DMAC_STA_REG': [48]}
INFO:root:'DMAC': Register block: (('N', (0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)),): {'DMAC_BCNT_LEFT_REGN': [280, 344, 408, 472, 536, 600, 664, 728, 792, 856, 920, 984, 1048, 1112, 1176, 1240], 'DMAC_CFG_REGN': [268, 332, 396, 460, 524, 588, 652, 716, 780, 844, 908, 972, 1036, 1100, 1164, 1228], 'DMAC_CUR_DEST_REGN': [276, 340, 404, 468, 532, 596, 660, 724, 788, 852, 916, 980, 1044, 1108, 1172, 1236], 'DMAC_CUR_SRC_REGN': [272, 336, 400, 464, 528, 592, 656, 720, 784, 848, 912, 976, 1040, 1104, 1168, 1232], 'DMAC_DESC_ADDR_REGN': [264, 328, 392, 456, 520, 584, 648, 712, 776, 840, 904, 968, 1032, 1096, 1160, 1224], 'DMAC_EN_REGN': [256, 320, 384, 448, 512, 576, 640, 704, 768, 832, 896, 960, 1024, 1088, 1152, 1216], 'DMAC_FDESC_ADDR_REGN': [300, 364, 428, 492, 556, 620, 684, 748, 812, 876, 940, 1004, 1068, 1132, 1196, 1260], 'DMAC_MODE_REGN': [296, 360, 424, 488, 552, 616, 680, 744, 808, 872, 936, 1000, 1064, 1128, 1192, 1256], 'DMAC_PARA_REGN': [284, 348, 412, 476, 540, 604, 668, 732, 796, 860, 924, 988, 1052, 1116, 1180, 1244], 'DMAC_PAU_REGN': [260, 324, 388, 452, 516, 580, 644, 708, 772, 836, 900, 964, 1028, 1092, 1156, 1220], 'DMAC_PKG_NUM_REGN': [304, 368, 432, 496, 560, 624, 688, 752, 816, 880, 944, 1008, 1072, 1136, 1200, 1264]}
WARNING:root:Could not interpret enumeratedValue '0': 'Idle' in field 'DMA_STATUS' in register 'DMAC_STA_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1': 'Busy' in field 'DMA_STATUS' in register 'DMAC_STA_REG' (num_bits = 16)
INFO:root:[('EMAC', '0x04500000   ')]: Automatically adding register 'EMAC_RX_DMA_LIST' even though it's not mentioned in the summary (note: this is working around a bug in the PDF)
INFO:root:[('EMAC', '0x04500000   ')]: Automatically adding register 'EMAC_TX_DMA_CUR_BUF' even though it's not mentioned in the summary (note: this is working around a bug in the PDF)
INFO:root:[('EMAC', '0x04500000   ')]: Automatically adding register 'EMAC_RX_DMA_CUR_DESC' even though it's not mentioned in the summary (note: this is working around a bug in the PDF)
INFO:root:[('EMAC', '0x04500000   ')]: Automatically adding register 'EMAC_TX_DMA_LIST' even though it's not mentioned in the summary (note: this is working around a bug in the PDF)
INFO:root:[('EMAC', '0x04500000   ')]: Automatically adding register 'EMAC_RX_DMA_CUR_BUF' even though it's not mentioned in the summary (note: this is working around a bug in the PDF)
INFO:root:[('EMAC', '0x04500000   ')]: Automatically adding register 'EMAC_TX_DMA_CUR_DESC' even though it's not mentioned in the summary (note: this is working around a bug in the PDF)
INFO:root:'EMAC': Register block: None: {'EMAC_ADDR_HIGH0': [80], 'EMAC_ADDR_LOW0': [84], 'EMAC_BASIC_CTL0': [0], 'EMAC_BASIC_CTL1': [4], 'EMAC_INT_EN': [12], 'EMAC_INT_STA': [8], 'EMAC_MII_CMD': [72], 'EMAC_MII_DATA': [76], 'EMAC_RGMII_STA': [208], 'EMAC_RX_CTL0': [36], 'EMAC_RX_CTL1': [40], 'EMAC_RX_DMA_CUR_BUF': [200], 'EMAC_RX_DMA_CUR_DESC': [196], 'EMAC_RX_DMA_LIST': [52], 'EMAC_RX_DMA_STA': [192], 'EMAC_RX_FRM_FLT': [56], 'EMAC_RX_HASH0': [64], 'EMAC_RX_HASH1': [68], 'EMAC_TX_CTL0': [16], 'EMAC_TX_CTL1': [20], 'EMAC_TX_DMA_CUR_BUF': [184], 'EMAC_TX_DMA_CUR_DESC': [180], 'EMAC_TX_DMA_LIST': [32], 'EMAC_TX_DMA_STA': [176], 'EMAC_TX_FLOW_CTL': [28]}
INFO:root:'EMAC': Register block: (('N', (1, 2, 3, 4, 5, 6, 7)),): {'EMAC_ADDR_HIGHN': [88, 96, 104, 112, 120, 128, 136], 'EMAC_ADDR_LOWN': [92, 100, 108, 116, 124, 132, 140]}
WARNING:root:register 'EMAC_RX_FRM_FLT' field 'CTL_FRM_FILTER' enum variants are not unique ([['00', ' Drop all control frames '], ['01', ' Drop all control frames '], ['10', ' Receive all control frames '], ['11', ' Receive all control frames when passing the address filter ']], counter = 5). Giving up.
WARNING:root:[['EMAC ', '0x04500000   ']]: Registers not used in any peripheral: ['EMAC_ADDR_HIGHN', 'EMAC_ADDR_LOWN']
WARNING:root:Could not interpret enumeratedValue '110': 'HS400 speed mode' in field 'CRC_DET_PARA' in register 'SMHC_CSDC' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue '011': 'Other speed mode' in field 'CRC_DET_PARA' in register 'SMHC_CSDC' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue '1x': '8-bit width' in field 'CARD_WID' in register 'SMHC_CTYPE' (num_bits = 2)
WARNING:root:Could not interpret enumeratedValue 'Others': 'Reserved  It  should  be  programmed  the  same  as  the  DMA  controller  multiple  transaction  size.  The  units  for  the  transfer  are  the  DWORD.  A  single  transfer  would  be  signaled  based  on  this  value.  The  value  should  be  sub-multiple  of  (RX_TL  +  1)  and  (FIFO_DEPTH - TX_TL)  Recommended:  FIFO_DEPTH = 256, FIFO_SIZE = 256 * 32 = 1K  MSize = 16, TX_TL = 240, RX_TL = 15' in field 'BSIZE_OF_TRANS' in register 'SMHC_FIFOTH' (num_bits = 3)
WARNING:root:Could not interpret enumeratedValue 'EBE': 'End Bit Error    RTO: Response Timeout    RCRC: Response CRC    SBE: Start Bit Error    DRTO: Data Read Timeout    DCRC: Data CRC for Receive    RE: Response Error    Writing 1 clears this bit.' in field 'ERR_FLAG_SUM' in register 'SMHC_IDST_REG' (num_bits = 1)
WARNING:root:register 'SMHC_NTSR' field 'CMD_SAMPLE_TIMING_PHASE' enum variants are not unique ([['00', ' Sample timing phase offset 90  '], ['01', ' Sample timing phase offset 180  '], ['10', ' Sample timing phase offset 270  '], ['11', ' Ignore ']], counter = 2). Giving up.
WARNING:root:register 'SMHC_STATUS' field 'FSM_STA' enum variants are not unique ([['0000', ' Idle '], ['0001', ' Send init sequence '], ['0010', ' TX CMD start bit '], ['0011', ' TX CMD TX bit '], ['0100', ' TX CMD index + argument '], ['0101', ' TX CMD CRC7 '], ['0110', ' TX CMD end bit '], ['0111', ' RX response start bit '], ['1000', ' RX response IRQ response '], ['1001', ' RX response TX bit '], ['1010', ' RX response CMD index '], ['1011', ' RX response data '], ['1100', ' RX response CRC7 '], ['1101', ' RX response end bit '], ['1110', ' CMD path wait NCC '], ['1111', ' Wait; CMD-to-response turn around ']], counter = 2). Giving up.
WARNING:root:'LCD_CTL_REG': Field names are not all known; for example the one described by: 'Set the interface type of LCD controller. \n00: HV(Sync+DE) \n01: 8080 I/F \n1x: Reserved '
INFO:root:'TCON_LCD0': Register block: None: {'FSYNC_GEN_CTRL_REG': [552], 'FSYNC_GEN_DLY_REG': [556], 'LCD_3D_FIFO_REG': [60], 'LCD_BASIC0_REG': [72], 'LCD_BASIC1_REG': [76], 'LCD_BASIC2_REG': [80], 'LCD_BASIC3_REG': [84], 'LCD_CEU_CTL_REG': [256], 'LCD_CMAP_CTL_REG': [384], 'LCD_CMAP_EVEN0_REG': [408], 'LCD_CMAP_EVEN1_REG': [412], 'LCD_CMAP_ODD0_REG': [400], 'LCD_CMAP_ODD1_REG': [404], 'LCD_CPU_IF_REG': [96], 'LCD_CPU_RD0_REG': [104], 'LCD_CPU_RD1_REG': [108], 'LCD_CPU_TRI0_REG': [352], 'LCD_CPU_TRI1_REG': [356], 'LCD_CPU_TRI2_REG': [360], 'LCD_CPU_TRI3_REG': [364], 'LCD_CPU_TRI4_REG': [368], 'LCD_CPU_TRI5_REG': [372], 'LCD_CPU_WR_REG': [100], 'LCD_CTL_REG': [64], 'LCD_DCLK_REG': [68], 'LCD_DEBUG_REG': [252], 'LCD_FRM_CTL_REG': [16], 'LCD_GCTL_REG': [0], 'LCD_GINT0_REG': [4], 'LCD_GINT1_REG': [8], 'LCD_HV_IF_REG': [88], 'LCD_IO_POL_REG': [136], 'LCD_IO_TRI_REG': [140], 'LCD_LVDS_ANA0_REG': [544], 'LCD_LVDS_IF_REG': [132], 'LCD_SAFE_PERIOD_REG': [496], 'LCD_SLAVE_STOP_POS_REG': [568], 'LCD_SYNC_CTL_REG': [560], 'LCD_SYNC_POS_REG': [564]}
INFO:root:'TCON_LCD0': Register block: (('N', (0, 1, 2)),): {'LCD_CEU_COEF_ADD_REG': [284, 300, 316], 'LCD_CEU_COEF_RANG_REG': [320, 324, 328]}
INFO:root:'TCON_LCD0': Register block: (('N', (0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10)),): {'LCD_CEU_COEF_MUL_REG': [272, 276, 280, 284, 288, 292, 296, 300, 304, 308, 312]}
INFO:root:'TCON_LCD0': Register block: (('N', (0, 1, 2, 3)),): {'LCD_FRM_TAB_REG': [44, 48, 52, 56]}
INFO:root:'TCON_LCD0': Register block: (('N', (0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212, 213, 214, 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228, 229, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, 241, 242, 243, 244, 245, 246, 247, 248, 249, 250, 251, 252, 253, 254, 255)),): {'LCD_GAMMA_TABLE_REG': [1024, 1028, 1032, 1036, 1040, 1044, 1048, 1052, 1056, 1060, 1064, 1068, 1072, 1076, 1080, 1084, 1088, 1092, 1096, 1100, 1104, 1108, 1112, 1116, 1120, 1124, 1128, 1132, 1136, 1140, 1144, 1148, 1152, 1156, 1160, 1164, 1168, 1172, 1176, 1180, 1184, 1188, 1192, 1196, 1200, 1204, 1208, 1212, 1216, 1220, 1224, 1228, 1232, 1236, 1240, 1244, 1248, 1252, 1256, 1260, 1264, 1268, 1272, 1276, 1280, 1284, 1288, 1292, 1296, 1300, 1304, 1308, 1312, 1316, 1320, 1324, 1328, 1332, 1336, 1340, 1344, 1348, 1352, 1356, 1360, 1364, 1368, 1372, 1376, 1380, 1384, 1388, 1392, 1396, 1400, 1404, 1408, 1412, 1416, 1420, 1424, 1428, 1432, 1436, 1440, 1444, 1448, 1452, 1456, 1460, 1464, 1468, 1472, 1476, 1480, 1484, 1488, 1492, 1496, 1500, 1504, 1508, 1512, 1516, 1520, 1524, 1528, 1532, 1536, 1540, 1544, 1548, 1552, 1556, 1560, 1564, 1568, 1572, 1576, 1580, 1584, 1588, 1592, 1596, 1600, 1604, 1608, 1612, 1616, 1620, 1624, 1628, 1632, 1636, 1640, 1644, 1648, 1652, 1656, 1660, 1664, 1668, 1672, 1676, 1680, 1684, 1688, 1692, 1696, 1700, 1704, 1708, 1712, 1716, 1720, 1724, 1728, 1732, 1736, 1740, 1744, 1748, 1752, 1756, 1760, 1764, 1768, 1772, 1776, 1780, 1784, 1788, 1792, 1796, 1800, 1804, 1808, 1812, 1816, 1820, 1824, 1828, 1832, 1836, 1840, 1844, 1848, 1852, 1856, 1860, 1864, 1868, 1872, 1876, 1880, 1884, 1888, 1892, 1896, 1900, 1904, 1908, 1912, 1916, 1920, 1924, 1928, 1932, 1936, 1940, 1944, 1948, 1952, 1956, 1960, 1964, 1968, 1972, 1976, 1980, 1984, 1988, 1992, 1996, 2000, 2004, 2008, 2012, 2016, 2020, 2024, 2028, 2032, 2036, 2040, 2044]}
INFO:root:'TCON_LCD0': Register block: (('N', (0, 1, 2, 3, 4, 5)),): {'xNx': [20, 24, 28, 32, 36, 40]}
WARNING:root:register 'LCD_3D_FIFO_REG' field '3D_FIFO' enum variants are not unique ([['00', ' Bypass '], ['01', ' Used as normal FIFO '], ['10', ' Used as 3D interlace FIFO '], ['11', ' Reserved   ']], counter = 2). Giving up.
WARNING:root:Could not interpret enumeratedValue '0000': 'in_b0' in field 'OUT_EVEN1' in register 'LCD_CMAP_EVEN0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0001': 'in_g0' in field 'OUT_EVEN1' in register 'LCD_CMAP_EVEN0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0010': 'in_r0' in field 'OUT_EVEN1' in register 'LCD_CMAP_EVEN0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0100': 'in_b1' in field 'OUT_EVEN1' in register 'LCD_CMAP_EVEN0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0101': 'in_g1' in field 'OUT_EVEN1' in register 'LCD_CMAP_EVEN0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0110': 'in_r1' in field 'OUT_EVEN1' in register 'LCD_CMAP_EVEN0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1000': 'in_b2' in field 'OUT_EVEN1' in register 'LCD_CMAP_EVEN0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1001': 'in_g2' in field 'OUT_EVEN1' in register 'LCD_CMAP_EVEN0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1010': 'in_r2' in field 'OUT_EVEN1' in register 'LCD_CMAP_EVEN0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1100': 'in_b3' in field 'OUT_EVEN1' in register 'LCD_CMAP_EVEN0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1101': 'in_g3' in field 'OUT_EVEN1' in register 'LCD_CMAP_EVEN0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1110': 'in_r3' in field 'OUT_EVEN1' in register 'LCD_CMAP_EVEN0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0000': 'in_b0' in field 'OUT_EVEN0' in register 'LCD_CMAP_EVEN0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0001': 'in_g0' in field 'OUT_EVEN0' in register 'LCD_CMAP_EVEN0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0010': 'in_r0' in field 'OUT_EVEN0' in register 'LCD_CMAP_EVEN0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0100': 'in_b1' in field 'OUT_EVEN0' in register 'LCD_CMAP_EVEN0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0101': 'in_g1' in field 'OUT_EVEN0' in register 'LCD_CMAP_EVEN0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0110': 'in_r1' in field 'OUT_EVEN0' in register 'LCD_CMAP_EVEN0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1000': 'in_b2' in field 'OUT_EVEN0' in register 'LCD_CMAP_EVEN0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1001': 'in_g2' in field 'OUT_EVEN0' in register 'LCD_CMAP_EVEN0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1010': 'in_r2' in field 'OUT_EVEN0' in register 'LCD_CMAP_EVEN0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1100': 'in_b3' in field 'OUT_EVEN0' in register 'LCD_CMAP_EVEN0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1101': 'in_g3' in field 'OUT_EVEN0' in register 'LCD_CMAP_EVEN0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1110': 'in_r3' in field 'OUT_EVEN0' in register 'LCD_CMAP_EVEN0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0000': 'in_b0' in field 'OUT_EVEN3' in register 'LCD_CMAP_EVEN1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0001': 'in_g0' in field 'OUT_EVEN3' in register 'LCD_CMAP_EVEN1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0010': 'in_r0' in field 'OUT_EVEN3' in register 'LCD_CMAP_EVEN1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0100': 'in_b1' in field 'OUT_EVEN3' in register 'LCD_CMAP_EVEN1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0101': 'in_g1' in field 'OUT_EVEN3' in register 'LCD_CMAP_EVEN1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0110': 'in_r1' in field 'OUT_EVEN3' in register 'LCD_CMAP_EVEN1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1000': 'in_b2' in field 'OUT_EVEN3' in register 'LCD_CMAP_EVEN1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1001': 'in_g2' in field 'OUT_EVEN3' in register 'LCD_CMAP_EVEN1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1010': 'in_r2' in field 'OUT_EVEN3' in register 'LCD_CMAP_EVEN1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1100': 'in_b3' in field 'OUT_EVEN3' in register 'LCD_CMAP_EVEN1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1101': 'in_g3' in field 'OUT_EVEN3' in register 'LCD_CMAP_EVEN1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1110': 'in_r3' in field 'OUT_EVEN3' in register 'LCD_CMAP_EVEN1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0000': 'in_b0' in field 'OUT_EVEN2' in register 'LCD_CMAP_EVEN1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0001': 'in_g0' in field 'OUT_EVEN2' in register 'LCD_CMAP_EVEN1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0010': 'in_r0' in field 'OUT_EVEN2' in register 'LCD_CMAP_EVEN1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0100': 'in_b1' in field 'OUT_EVEN2' in register 'LCD_CMAP_EVEN1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0101': 'in_g1' in field 'OUT_EVEN2' in register 'LCD_CMAP_EVEN1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0110': 'in_r1' in field 'OUT_EVEN2' in register 'LCD_CMAP_EVEN1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1000': 'in_b2' in field 'OUT_EVEN2' in register 'LCD_CMAP_EVEN1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1001': 'in_g2' in field 'OUT_EVEN2' in register 'LCD_CMAP_EVEN1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1010': 'in_r2' in field 'OUT_EVEN2' in register 'LCD_CMAP_EVEN1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1100': 'in_b3' in field 'OUT_EVEN2' in register 'LCD_CMAP_EVEN1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1101': 'in_g3' in field 'OUT_EVEN2' in register 'LCD_CMAP_EVEN1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1110': 'in_r3' in field 'OUT_EVEN2' in register 'LCD_CMAP_EVEN1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0000': 'in_b0' in field 'OUT_ODD1' in register 'LCD_CMAP_ODD0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0001': 'in_g0' in field 'OUT_ODD1' in register 'LCD_CMAP_ODD0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0010': 'in_r0' in field 'OUT_ODD1' in register 'LCD_CMAP_ODD0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0100': 'in_b1' in field 'OUT_ODD1' in register 'LCD_CMAP_ODD0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0101': 'in_g1' in field 'OUT_ODD1' in register 'LCD_CMAP_ODD0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0110': 'in_r1' in field 'OUT_ODD1' in register 'LCD_CMAP_ODD0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1000': 'in_b2' in field 'OUT_ODD1' in register 'LCD_CMAP_ODD0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1001': 'in_g2' in field 'OUT_ODD1' in register 'LCD_CMAP_ODD0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1010': 'in_r2' in field 'OUT_ODD1' in register 'LCD_CMAP_ODD0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1100': 'in_b3' in field 'OUT_ODD1' in register 'LCD_CMAP_ODD0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1101': 'in_g3' in field 'OUT_ODD1' in register 'LCD_CMAP_ODD0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1110': 'in_r3' in field 'OUT_ODD1' in register 'LCD_CMAP_ODD0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0000': 'in_b0' in field 'OUT_ODD0' in register 'LCD_CMAP_ODD0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0001': 'in_g0' in field 'OUT_ODD0' in register 'LCD_CMAP_ODD0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0010': 'in_r0' in field 'OUT_ODD0' in register 'LCD_CMAP_ODD0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0100': 'in_b1' in field 'OUT_ODD0' in register 'LCD_CMAP_ODD0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0101': 'in_g1' in field 'OUT_ODD0' in register 'LCD_CMAP_ODD0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0110': 'in_r1' in field 'OUT_ODD0' in register 'LCD_CMAP_ODD0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1000': 'in_b2' in field 'OUT_ODD0' in register 'LCD_CMAP_ODD0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1001': 'in_g2' in field 'OUT_ODD0' in register 'LCD_CMAP_ODD0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1010': 'in_r2' in field 'OUT_ODD0' in register 'LCD_CMAP_ODD0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1100': 'in_b3' in field 'OUT_ODD0' in register 'LCD_CMAP_ODD0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1101': 'in_g3' in field 'OUT_ODD0' in register 'LCD_CMAP_ODD0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1110': 'in_r3' in field 'OUT_ODD0' in register 'LCD_CMAP_ODD0_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0000': 'in_b0' in field 'OUT_ODD3' in register 'LCD_CMAP_ODD1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0001': 'in_g0' in field 'OUT_ODD3' in register 'LCD_CMAP_ODD1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0010': 'in_r0' in field 'OUT_ODD3' in register 'LCD_CMAP_ODD1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0100': 'in_b1' in field 'OUT_ODD3' in register 'LCD_CMAP_ODD1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0101': 'in_g1' in field 'OUT_ODD3' in register 'LCD_CMAP_ODD1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0110': 'in_r1' in field 'OUT_ODD3' in register 'LCD_CMAP_ODD1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1000': 'in_b2' in field 'OUT_ODD3' in register 'LCD_CMAP_ODD1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1001': 'in_g2' in field 'OUT_ODD3' in register 'LCD_CMAP_ODD1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1010': 'in_r2' in field 'OUT_ODD3' in register 'LCD_CMAP_ODD1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1100': 'in_b3' in field 'OUT_ODD3' in register 'LCD_CMAP_ODD1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1101': 'in_g3' in field 'OUT_ODD3' in register 'LCD_CMAP_ODD1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1110': 'in_r3' in field 'OUT_ODD3' in register 'LCD_CMAP_ODD1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0000': 'in_b0' in field 'OUT_ODD2' in register 'LCD_CMAP_ODD1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0001': 'in_g0' in field 'OUT_ODD2' in register 'LCD_CMAP_ODD1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0010': 'in_r0' in field 'OUT_ODD2' in register 'LCD_CMAP_ODD1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0100': 'in_b1' in field 'OUT_ODD2' in register 'LCD_CMAP_ODD1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0101': 'in_g1' in field 'OUT_ODD2' in register 'LCD_CMAP_ODD1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '0110': 'in_r1' in field 'OUT_ODD2' in register 'LCD_CMAP_ODD1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1000': 'in_b2' in field 'OUT_ODD2' in register 'LCD_CMAP_ODD1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1001': 'in_g2' in field 'OUT_ODD2' in register 'LCD_CMAP_ODD1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1010': 'in_r2' in field 'OUT_ODD2' in register 'LCD_CMAP_ODD1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1100': 'in_b3' in field 'OUT_ODD2' in register 'LCD_CMAP_ODD1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1101': 'in_g3' in field 'OUT_ODD2' in register 'LCD_CMAP_ODD1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue '1110': 'in_r3' in field 'OUT_ODD2' in register 'LCD_CMAP_ODD1_REG' (num_bits = 16)
WARNING:root:Could not interpret enumeratedValue 'xxx1': '24-bit for DSI' in field 'CPU_MODE' in register 'LCD_CPU_IF_REG' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue '0x': 'Auto' in field 'SYNC_MODE' in register 'LCD_CPU_TRI2_REG'
WARNING:root:register 'LCD_CPU_TRI3_REG' field 'TRI_INT_MODE' enum variants are not unique ([['00', ' Disable '], ['01', ' Counter mode   '], ['10', ' Te rising mode '], ['11', ' Te falling mode ']], counter = 2). Giving up.
WARNING:root:register 'LCD_CTL_REG' field 'LCD_SRC_SEL' enum variants are not unique ([['000', ' DE '], ['001', ' Color Check '], ['010', ' Grayscale Check '], ['011', ' Black by White Check '], ['100', ' Test Data all 0 '], ['101', ' Test Data all 1 '], ['110', ' Reversed '], ['111', ' Gridding Check       ']], counter = 2). Giving up.
WARNING:root:register 'LCD_DCLK_REG' field 'LCD_DCLK_EN' enum variants are not unique ([('0000', ' dclk_en = 0; dclk1_en = 0; dclk2_en = 0; dclkm2_en = 0;                           '), ('0001', ' dclk_en = 1; dclk1_en = 0; dclk2_en = 0; dclkm2_en = 0;                         '), ('0010', ' dclk_en = 1; dclk1_en = 0; dclk2_en = 0; dclkm2_en = 1;                         '), ('0011', ' dclk_en = 1; dclk1_en = 1; dclk2_en = 0; dclkm2_en = 0;                         '), ('0101', ' dclk_en = 1; dclk1_en = 0; dclk2_en = 1; dclkm2_en = 0;                         '), ('1111', ' dclk_en = 1; dclk1_en = 1; dclk2_en = 1; dclkm2_en = 1;  '), ('Others', 'Reversed ')], counter = 2). Giving up.
WARNING:root:register 'LCD_FRM_CTL_REG' field 'LCD_FRM_TEST' enum variants are not unique ([['00', ' FRM '], ['01', ' Half 5-/6-bit, half FRM '], ['10', ' Half 8-bit, half FRM '], ['11', ' Half 8-bit, half 5-/6-bit   ']], counter = 2). Giving up.
WARNING:root:register 'LCD_HV_IF_REG' field 'RGB888_ODD_ORDER' enum variants are not unique ([['00', ' R→G→B '], ['01', ' B→R→G '], ['10', ' G→B→R '], ['11', ' R→G→B ']], counter = 2). Giving up.
WARNING:root:register 'LCD_HV_IF_REG' field 'RGB888_EVEN_ORDER' enum variants are not unique ([['00', ' R→G→B '], ['01', ' B→R→G '], ['10', ' G→B→R '], ['11', ' R→G→B ']], counter = 2). Giving up.
WARNING:root:Could not interpret enumeratedValue '0': 'Normal polarity' in field 'DATA_INV' in register 'LCD_IO_POL_REG' (num_bits = 24)
WARNING:root:Could not interpret enumeratedValue '1': 'Invert the specify output' in field 'DATA_INV' in register 'LCD_IO_POL_REG' (num_bits = 24)
WARNING:root:Could not interpret enumeratedValue '1': 'Disable' in field 'DATA_OUTPUT_TRI_EN' in register 'LCD_IO_TRI_REG' (num_bits = 24)
WARNING:root:Could not interpret enumeratedValue '0': 'Enable' in field 'DATA_OUTPUT_TRI_EN' in register 'LCD_IO_TRI_REG' (num_bits = 24)
WARNING:root:Could not interpret enumeratedValue '0': 'Disable' in field 'LVDS_HPREN_DRV' in register 'LCD_LVDS_ANA0_REG' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue '1': 'Enable' in field 'LVDS_HPREN_DRV' in register 'LCD_LVDS_ANA0_REG' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue '0': 'Normal' in field 'LVDS_REG_PLR' in register 'LCD_LVDS_ANA0_REG' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue '1': 'Reverse' in field 'LVDS_REG_PLR' in register 'LCD_LVDS_ANA0_REG' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue '0': 'Reverse' in field 'LCD_LVDS_DATA_POL' in register 'LCD_LVDS_IF_REG' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue '1': 'Normal' in field 'LCD_LVDS_DATA_POL' in register 'LCD_LVDS_IF_REG' (num_bits = 4)
WARNING:root:register 'LCD_SAFE_PERIOD_REG' field 'SAFE_PERIOD_MODE' enum variants are not unique ([['000', ' unsafe '], ['001', ' safe '], ['010', ' safe at FIFO_CURR_NUM > SAFE_PERIOD_FIFO_NUM '], ['011', ' safe at 2 and safe at sync active '], ['100', ' safe at line   ']], counter = 2). Giving up.
WARNING:root:'GP_CTRL': Invalid field ['31:24  R/', 'W', '0x0   ', 'ADC_FIRST_DLY  ADC First Convert Delay Setting  ADC conversion of each channel is delayed by N samples. ']: Bitrange error
WARNING:root:'HS_TMR0_CURNT_HI_REG': Invalid field ['HSTimer0 is a 56-bit counter. The current value consists of two parts: HS_TMR0_CUR_VALUE_LO acts as the', '', '', '']: Bitrange error
WARNING:root:Field could not be parsed as a bitrange: ['bit[31', '0]  and  HS_TMR0_CUR_VALUE_HI  acts  as  the  bit[55', '32].  To  read  or  write  the  current  value,']
WARNING:root:'HS_TMR0_CURNT_HI_REG': Invalid field ['HS_TMR0_CUR_VALUE_LO should be done before HS_TMR0_CUR_VALUE_HI.', '', '', '']: Bitrange error
WARNING:root:'HS_TMR0_INTV_HI_REG': Invalid field ['HSTimer0 is a 56-bit counter. The interval value consists of two parts: HS_TMR0_INTV_VALUE_LO acts as', '', '', '']: Bitrange error
WARNING:root:Field could not be parsed as a bitrange: ['the  bit[31', '0]  and  HS_TMR0_INTV_VALUE_HI  acts  as  the  bit[55', '32].  To  read  or  write  the  interval  value,']
WARNING:root:'HS_TMR0_INTV_HI_REG': Invalid field ['HS_TMR0_INTV_LO_REG should be done before HS_TMR0_INTV_HI_REG.', '', '', '']: Bitrange error
WARNING:root:'HS_TMR1_CURNT_HI_REG': Invalid field ['HSTimer1 is a 56-bit counter. The current value consists of two parts: HS_TMR1_CUR_VALUE_LO acts as the', '', '', '']: Bitrange error
WARNING:root:Field could not be parsed as a bitrange: ['bit[31', '0]  and  HS_TMR1_CUR_VALUE_HI  acts  as  the  bit[55', '32].  To  read  or  write  the  current  value,']
WARNING:root:'HS_TMR1_CURNT_HI_REG': Invalid field ['HS_TMR1_CUR_VALUE_LO should be done before HS_TMR1_CUR_VALUE_HI.', '', '', '']: Bitrange error
WARNING:root:'HS_TMR1_INTV_HI_REG': Invalid field ['HSTimer1 is a 56-bit counter. The interval value consists of two parts: HS_TMR1_INTV_VALUE_LO acts as', '', '', '']: Bitrange error
WARNING:root:Field could not be parsed as a bitrange: ['the  bit[31', '0]  and  HS_TMR1_INTV_VALUE_HI  acts  as  the  bit[55', '32].  To  read  or  write  the  interval  value,']
WARNING:root:'HS_TMR1_INTV_HI_REG': Invalid field ['HS_TMR1_INTV_LO_REG should be done before HS_TMR1_INTV_HI_REG.', '', '', '']: Bitrange error
WARNING:root:Could not interpret enumeratedValue '0': 'High-level trigger' in field 'IRQ_MD0' in register 'IRQ_MODE0_REG' (num_bits = 32)
WARNING:root:Could not interpret enumeratedValue '1': 'Rising edge trigger' in field 'IRQ_MD0' in register 'IRQ_MODE0_REG' (num_bits = 32)
WARNING:root:Could not interpret enumeratedValue '0': 'High-level trigger' in field 'IRQ_MD1' in register 'IRQ_MODE1_REG' (num_bits = 32)
WARNING:root:Could not interpret enumeratedValue '1': 'Rising edge trigger' in field 'IRQ_MD1' in register 'IRQ_MODE1_REG' (num_bits = 32)
WARNING:root:Could not interpret enumeratedValue '0': 'High-level trigger' in field 'IRQ_MD2' in register 'IRQ_MODE2_REG' (num_bits = 32)
WARNING:root:Could not interpret enumeratedValue '1': 'Rising edge trigger' in field 'IRQ_MD2' in register 'IRQ_MODE2_REG' (num_bits = 32)
WARNING:root:Could not interpret enumeratedValue '0': 'High-level trigger' in field 'IRQ_MD3' in register 'IRQ_MODE3_REG' (num_bits = 32)
WARNING:root:Could not interpret enumeratedValue '1': 'Rising edge trigger' in field 'IRQ_MD3' in register 'IRQ_MODE3_REG' (num_bits = 32)
WARNING:root:Could not interpret enumeratedValue '0': 'High-level trigger' in field 'IRQ_MD4' in register 'IRQ_MODE4_REG' (num_bits = 32)
WARNING:root:Could not interpret enumeratedValue '1': 'Rising edge trigger' in field 'IRQ_MD4' in register 'IRQ_MODE4_REG' (num_bits = 32)
INFO:root:'LEDC': Register block: None: {'LEDC_CTRL_REG': [0], 'LEDC_DATA_FINISH_CNT_REG': [8], 'LEDC_DATA_REG': [20], 'LEDC_DMA_CTRL_REG': [24], 'LEDC_INTERRUPT_CTRL_REG': [28], 'LEDC_INT_STS_REG': [32], 'LEDC_WAIT_TIME0_CTRL_REG': [16], 'LEDC_WAIT_TIME1_CTRL_REG': [40], 'LED_RESET_TIMING_CTRL_REG': [12], 'LED_T01_TIMING_CTRL_REG': [4]}
INFO:root:'LEDC': Register block: (('N', (0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31)),): {'LEDC_FIFO_DATA_X': [48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92, 96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 148, 152, 156, 160, 164, 168, 172]}
INFO:root:'DSP_MSGBOX': Register block: None: {}
INFO:root:'DSP_MSGBOX': Register block: (('N', (0, 1)), ('P', (0, 1, 2, 3))): {'MSGBOX_FIFO_STATUS_REG': [80, 336], 'MSGBOX_MSG_REG': [112, 368], 'MSGBOX_MSG_STATUS_REG': [96, 352], 'MSGBOX_WR_INT_THRESHOLD_REG': [128, 384]}
INFO:root:'DSP_MSGBOX': Register block: (('N', (0, 1)),): {'MSGBOX_RD_IRQ_EN_REG': [32, 288], 'MSGBOX_RD_IRQ_STATUS_REG': [36, 292], 'MSGBOX_WR_IRQ_EN_REG': [48, 304], 'MSGBOX_WR_IRQ_STATUS_REG': [52, 308]}
WARNING:root:'OWA_TX_CHSTA1': Field names are not all known; for example the one described by: '00: Copying is permitted without restriction \n01: One generation of copies may be made \n10: Condition not be used \n11: No copying is permitted '
WARNING:root:register 'OWA_TX_CHSTA0' field 'EMP' enum variants are not unique ([['000', ' 2 audio channels without pre-emphasis '], ['001', ' 2 audio channels with 50 μs/15 μs pre-emphasis '], ['010', ' Reserved (for 2 audio channels with pre-emphasis) '], ['011', ' Reserved (for 2 audio channels with pre-emphasis)  100 to 111: Reserved  For bit 1 = “1”, other than Linear PCM applications: '], ['000', ' Default state  001 to 111: Reserved ']], counter = 6). Giving up.
WARNING:root:register 'OWA_TX_CHSTA1' field 'WL' enum variants are not unique ([['000', ' Not indicated '], ['001', ' 16 bits '], ['010', ' 18 bits '], ['100', ' 19 bits '], ['101', ' 20 bits '], ['110', ' 17 bits '], ['111', ' Reserved  For bit 0 = “1”: '], ['000', ' Not indicated '], ['001', ' 20 bits '], ['010', ' 22 bits '], ['100', ' 23 bits '], ['101', ' 24 bits '], ['110', ' 21 bits '], ['111', ' Reserved ']], counter = 3). Giving up.
INFO:root:'RISCV PLIC': Register block: None: {'PLIC_CTRL_REG': [2097148], 'PLIC_MCLAIM_REG': [2097156], 'PLIC_MTH_REG': [2097152], 'PLIC_SCLAIM_REG': [2101252], 'PLIC_STH_REG': [2101248]}
INFO:root:'RISCV PLIC': Register block: (('n', (0, 1, 2, 3, 4, 5, 6, 7, 8)),): {'PLIC_IP_REGn': [4096, 4100, 4104, 4108, 4112, 4116, 4120, 4124, 4128], 'PLIC_MIE_REGn': [8192, 8196, 8200, 8204, 8208, 8212, 8216, 8220, 8224], 'PLIC_SIE_REGn': [8320, 8324, 8328, 8332, 8336, 8340, 8344, 8348, 8352]}
INFO:root:'RISCV PLIC': Register block: (('n', (1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212, 213, 214, 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228, 229, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, 241, 242, 243, 244, 245, 246, 247, 248, 249, 250, 251, 252, 253, 254, 255)),): {'PLIC_PRIO_REGn': [4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92, 96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 148, 152, 156, 160, 164, 168, 172, 176, 180, 184, 188, 192, 196, 200, 204, 208, 212, 216, 220, 224, 228, 232, 236, 240, 244, 248, 252, 256, 260, 264, 268, 272, 276, 280, 284, 288, 292, 296, 300, 304, 308, 312, 316, 320, 324, 328, 332, 336, 340, 344, 348, 352, 356, 360, 364, 368, 372, 376, 380, 384, 388, 392, 396, 400, 404, 408, 412, 416, 420, 424, 428, 432, 436, 440, 444, 448, 452, 456, 460, 464, 468, 472, 476, 480, 484, 488, 492, 496, 500, 504, 508, 512, 516, 520, 524, 528, 532, 536, 540, 544, 548, 552, 556, 560, 564, 568, 572, 576, 580, 584, 588, 592, 596, 600, 604, 608, 612, 616, 620, 624, 628, 632, 636, 640, 644, 648, 652, 656, 660, 664, 668, 672, 676, 680, 684, 688, 692, 696, 700, 704, 708, 712, 716, 720, 724, 728, 732, 736, 740, 744, 748, 752, 756, 760, 764, 768, 772, 776, 780, 784, 788, 792, 796, 800, 804, 808, 812, 816, 820, 824, 828, 832, 836, 840, 844, 848, 852, 856, 860, 864, 868, 872, 876, 880, 884, 888, 892, 896, 900, 904, 908, 912, 916, 920, 924, 928, 932, 936, 940, 944, 948, 952, 956, 960, 964, 968, 972, 976, 980, 984, 988, 992, 996, 1000, 1004, 1008, 1012, 1016, 1020]}
WARNING:root:'SPINLOCK_LOCKIN0_REG': Default '77777777  LOCKID0' for field ['31:0', 'R ', '0x77777777  LOCKID0 ', ''] was not understood
WARNING:root:'SPINLOCK_LOCKIN0_REG': Default '77777777  LOCKID0' for field ['31:0', 'R ', '0x77777777  LOCKID0 ', ''] was not understood
WARNING:root:'SPINLOCK_LOCKIN0_REG': Default '77777777  LOCKID0' for field ['31:0', 'R ', '0x77777777  LOCKID0 ', ''] was not understood
WARNING:root:'SPINLOCK_LOCKIN0_REG': Default '77777777  LOCKID0' for field ['31:0', 'R ', '0x77777777  LOCKID0 ', ''] was not understood
WARNING:root:'SPINLOCK_LOCKIN0_REG': Default '77777777  LOCKID0' for field ['31:0', 'R ', '0x77777777  LOCKID0 ', ''] was not understood
WARNING:root:'SPINLOCK_LOCKIN0_REG': Default '77777777  LOCKID0' for field ['31:0', 'R ', '0x77777777  LOCKID0 ', ''] was not understood
WARNING:root:'SPINLOCK_LOCKIN0_REG': Field name could not be determined: ['31:0', 'R ', '0x77777777  LOCKID0 ', ''] (tried: '')
WARNING:root:'SPINLOCK_LOCKIN1_REG': Default '77777777  LOCKID1' for field ['31:0', 'R ', '0x77777777  LOCKID1 ', ''] was not understood
WARNING:root:'SPINLOCK_LOCKIN1_REG': Default '77777777  LOCKID1' for field ['31:0', 'R ', '0x77777777  LOCKID1 ', ''] was not understood
WARNING:root:'SPINLOCK_LOCKIN1_REG': Default '77777777  LOCKID1' for field ['31:0', 'R ', '0x77777777  LOCKID1 ', ''] was not understood
WARNING:root:'SPINLOCK_LOCKIN1_REG': Default '77777777  LOCKID1' for field ['31:0', 'R ', '0x77777777  LOCKID1 ', ''] was not understood
WARNING:root:'SPINLOCK_LOCKIN1_REG': Default '77777777  LOCKID1' for field ['31:0', 'R ', '0x77777777  LOCKID1 ', ''] was not understood
WARNING:root:'SPINLOCK_LOCKIN1_REG': Default '77777777  LOCKID1' for field ['31:0', 'R ', '0x77777777  LOCKID1 ', ''] was not understood
WARNING:root:'SPINLOCK_LOCKIN1_REG': Field name could not be determined: ['31:0', 'R ', '0x77777777  LOCKID1 ', ''] (tried: '')
WARNING:root:'SPINLOCK_LOCKIN2_REG': Default '77777777  LOCKID2' for field ['31:0', 'R ', '0x77777777  LOCKID2 ', ''] was not understood
WARNING:root:'SPINLOCK_LOCKIN2_REG': Default '77777777  LOCKID2' for field ['31:0', 'R ', '0x77777777  LOCKID2 ', ''] was not understood
WARNING:root:'SPINLOCK_LOCKIN2_REG': Default '77777777  LOCKID2' for field ['31:0', 'R ', '0x77777777  LOCKID2 ', ''] was not understood
WARNING:root:'SPINLOCK_LOCKIN2_REG': Default '77777777  LOCKID2' for field ['31:0', 'R ', '0x77777777  LOCKID2 ', ''] was not understood
WARNING:root:'SPINLOCK_LOCKIN2_REG': Default '77777777  LOCKID2' for field ['31:0', 'R ', '0x77777777  LOCKID2 ', ''] was not understood
WARNING:root:'SPINLOCK_LOCKIN2_REG': Default '77777777  LOCKID2' for field ['31:0', 'R ', '0x77777777  LOCKID2 ', ''] was not understood
WARNING:root:'SPINLOCK_LOCKIN2_REG': Field name could not be determined: ['31:0', 'R ', '0x77777777  LOCKID2 ', ''] (tried: '')
WARNING:root:'SPINLOCK_LOCKIN3_REG': Default '77777777  LOCKID3' for field ['31:0', 'R ', '0x77777777  LOCKID3 ', ''] was not understood
WARNING:root:'SPINLOCK_LOCKIN3_REG': Default '77777777  LOCKID3' for field ['31:0', 'R ', '0x77777777  LOCKID3 ', ''] was not understood
WARNING:root:'SPINLOCK_LOCKIN3_REG': Default '77777777  LOCKID3' for field ['31:0', 'R ', '0x77777777  LOCKID3 ', ''] was not understood
WARNING:root:'SPINLOCK_LOCKIN3_REG': Default '77777777  LOCKID3' for field ['31:0', 'R ', '0x77777777  LOCKID3 ', ''] was not understood
WARNING:root:'SPINLOCK_LOCKIN3_REG': Default '77777777  LOCKID3' for field ['31:0', 'R ', '0x77777777  LOCKID3 ', ''] was not understood
WARNING:root:'SPINLOCK_LOCKIN3_REG': Default '77777777  LOCKID3' for field ['31:0', 'R ', '0x77777777  LOCKID3 ', ''] was not understood
WARNING:root:'SPINLOCK_LOCKIN3_REG': Field name could not be determined: ['31:0', 'R ', '0x77777777  LOCKID3 ', ''] (tried: '')
WARNING:root:'SPINLOCK_LOCKIN4_REG': Default '77777777  LOCKID4' for field ['31:0', 'R ', '0x77777777  LOCKID4 ', ''] was not understood
WARNING:root:'SPINLOCK_LOCKIN4_REG': Default '77777777  LOCKID4' for field ['31:0', 'R ', '0x77777777  LOCKID4 ', ''] was not understood
WARNING:root:'SPINLOCK_LOCKIN4_REG': Default '77777777  LOCKID4' for field ['31:0', 'R ', '0x77777777  LOCKID4 ', ''] was not understood
WARNING:root:'SPINLOCK_LOCKIN4_REG': Default '77777777  LOCKID4' for field ['31:0', 'R ', '0x77777777  LOCKID4 ', ''] was not understood
WARNING:root:'SPINLOCK_LOCKIN4_REG': Default '77777777  LOCKID4' for field ['31:0', 'R ', '0x77777777  LOCKID4 ', ''] was not understood
WARNING:root:'SPINLOCK_LOCKIN4_REG': Default '77777777  LOCKID4' for field ['31:0', 'R ', '0x77777777  LOCKID4 ', ''] was not understood
WARNING:root:'SPINLOCK_LOCKIN4_REG': Field name could not be determined: ['31:0', 'R ', '0x77777777  LOCKID4 ', ''] (tried: '')
INFO:root:'Spinlock': Register block: None: {'SPINLOCK_IRQ_EN_REG': [32], 'SPINLOCK_IRQ_STA_REG': [64], 'SPINLOCK_LOCKIN0_REG': [128], 'SPINLOCK_LOCKIN1_REG': [132], 'SPINLOCK_LOCKIN2_REG': [136], 'SPINLOCK_LOCKIN3_REG': [140], 'SPINLOCK_LOCKIN4_REG': [144], 'SPINLOCK_STATUS_REG': [16], 'SPINLOCK_SYSTATUS_REG': [0]}
INFO:root:'Spinlock': Register block: (('N', (0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31)),): {'SPINLOCKN_LOCK_REG': [256, 260, 264, 268, 272, 276, 280, 284, 288, 292, 296, 300, 304, 308, 312, 316, 320, 324, 328, 332, 336, 340, 344, 348, 352, 356, 360, 364, 368, 372, 376, 380]}
WARNING:root:Could not interpret enumeratedValue '0': 'Disable' in field 'LOCK_IRQ_EN' in register 'SPINLOCK_IRQ_EN_REG' (num_bits = 32)
WARNING:root:Could not interpret enumeratedValue '1': 'Enable' in field 'LOCK_IRQ_EN' in register 'SPINLOCK_IRQ_EN_REG' (num_bits = 32)
WARNING:root:Could not interpret enumeratedValue '0': 'No effect' in field 'LOCK_IRQ_STATUS' in register 'SPINLOCK_IRQ_STA_REG' (num_bits = 32)
WARNING:root:Could not interpret enumeratedValue '1': 'Pending  Writing 1 clears this bit.' in field 'LOCK_IRQ_STATUS' in register 'SPINLOCK_IRQ_STA_REG' (num_bits = 32)
WARNING:root:Could not interpret enumeratedValue '0': 'The Spinlock is free' in field 'LOCK_REG_STATUS' in register 'SPINLOCK_STATUS_REG' (num_bits = 32)
WARNING:root:Could not interpret enumeratedValue '1': 'The Spinlock is taken' in field 'LOCK_REG_STATUS' in register 'SPINLOCK_STATUS_REG' (num_bits = 32)
WARNING:root:register 'TP_CTRL0' field 'FS_DIV' enum variants are not unique ([['0000', ' CLK_IN/2  '], ['0001', ' CLK_IN/2  '], ['0010', ' CLK_IN/2   ….   '], ['1111', ' CLK_IN/2  ']], counter = 2). Giving up.
INFO:root:'TVD_TOP': Register block: None: {'TVD_3D_CTL1': [8], 'TVD_3D_CTL2': [12], 'TVD_3D_CTL3': [16], 'TVD_3D_CTL4': [20], 'TVD_3D_CTL5': [24], 'TVD_TOP_MAP': [0]}
INFO:root:'TVD_TOP': Register block: (('N', (0, 1, 2, 3)),): {'TVD_ADC_CFG': [44, 76, 108, 140], 'TVD_ADC_CTL': [40, 72, 104, 136], 'TVD_TOP_CTL': [36, 68, 100, 132]}
WARNING:root:register 'TVD_CLOCK1' field 'COLOR_STD' enum variants are not unique ([['000', ' NTSC '], ['001', ' PAL (I,B,G,H,D,N) '], ['010', ' PAL (M) '], ['011', ' PAL (CN) '], ['100', ' SECAM ']], counter = 2). Giving up.
WARNING:root:Could not interpret enumeratedValue '0': '858' in field 'HTOL' in register 'TVD_HLOCK2' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue '1': '864  2~7: Reserved' in field 'HTOL' in register 'TVD_HLOCK2' (num_bits = 4)
WARNING:root:register 'TVD_YC_SEP1' field '3D_COMB_FILTER_MODE' enum variants are not unique ([['000', ' 2D mode '], ['001', ' 3D YC separation mode1  010~011: reserved '], ['0100', ' 3D YC separation mode2   ']], counter = 3). Giving up.
WARNING:root:[['TVD_TOP ', '0x05C00000 '], ['TVD0 ', '0x05C01000   ']]: Registers not used in any peripheral: ['TVD_ADC_CFG', 'TVD_ADC_CTL', 'TVD_TOP_CTL']
WARNING:root:register 'TVE_004_REG' field 'DAC_SRC_SEL' enum variants are not unique ([['00', ' TV Encoder '], ['01', ' LCD controller, override all other TV encoder setting, the  DAC clock can from LCD controller. '], ['10', ' DAC test mode, DAC using DAC clock '], ['11', ' DAC test mode, DAC using AHB clock ']], counter = 3). Giving up.
WARNING:root:Could not interpret enumeratedValue '111x': 'Reserved  Note:  Changing  this  register  value  will  cause  some  relative  register setting to relative value.' in field 'TVMODE_SELECT' in register 'TVE_004_REG' (num_bits = 4)
INFO:root:'TCON_TV0': Register block: None: {'TV_BASIC0_REG': [148], 'TV_BASIC1_REG': [152], 'TV_BASIC2_REG': [156], 'TV_BASIC3_REG': [160], 'TV_BASIC4_REG': [164], 'TV_BASIC5_REG': [168], 'TV_CEU_CTL_REG': [256], 'TV_CTL_REG': [144], 'TV_DATA_IO_POL0_REG': [816], 'TV_DATA_IO_POL1_REG': [820], 'TV_DATA_IO_TRI0_REG': [824], 'TV_DATA_IO_TRI1_REG': [828], 'TV_DEBUG_REG': [252], 'TV_FILL_CTL_REG': [768], 'TV_GCTL_REG': [0], 'TV_GINT0_REG': [4], 'TV_GINT1_REG': [8], 'TV_IO_POL_REG': [136], 'TV_IO_TRI_REG': [140], 'TV_PIXELDEPTH_MODE_REG': [832], 'TV_SAFE_PERIOD_REG': [496], 'TV_SRC_CTL_REG': [64]}
INFO:root:'TCON_TV0': Register block: (('N', (0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10)),): {'TV_CEU_COEF_MUL_REG': [272, 276, 280, 284, 288, 292, 296, 300, 304, 308, 312]}
INFO:root:'TCON_TV0': Register block: (('N', (0, 1, 2)),): {'TV_CEU_COEF_RANG_REG': [320, 324, 328], 'TV_FILL_BEGIN_REG': [772, 784, 796], 'TV_FILL_DATA_REG': [780, 792, 804], 'TV_FILL_END_REG': [776, 788, 800]}
WARNING:root:Could not interpret enumeratedValue '0': 'normal polarity' in field 'R_CB_CH_DATA_INV' in register 'TV_DATA_IO_POL0_REG' (num_bits = 10)
WARNING:root:Could not interpret enumeratedValue '1': 'invert the specify output' in field 'R_CB_CH_DATA_INV' in register 'TV_DATA_IO_POL0_REG' (num_bits = 10)
WARNING:root:Could not interpret enumeratedValue '0': 'normal polarity' in field 'G_Y_CH_DATA_INV' in register 'TV_DATA_IO_POL0_REG' (num_bits = 10)
WARNING:root:Could not interpret enumeratedValue '1': 'invert the specify output' in field 'G_Y_CH_DATA_INV' in register 'TV_DATA_IO_POL0_REG' (num_bits = 10)
WARNING:root:Could not interpret enumeratedValue '0': 'Normal polarity' in field 'B_CR_CH_DATA_INV' in register 'TV_DATA_IO_POL1_REG' (num_bits = 10)
WARNING:root:Could not interpret enumeratedValue '1': 'Invert the specify output' in field 'B_CR_CH_DATA_INV' in register 'TV_DATA_IO_POL1_REG' (num_bits = 10)
WARNING:root:Could not interpret enumeratedValue '1': 'Disable' in field 'R_CB_CH_DATA_OUT_TRI_EN' in register 'TV_DATA_IO_TRI0_REG' (num_bits = 10)
WARNING:root:Could not interpret enumeratedValue '0': 'Enable' in field 'R_CB_CH_DATA_OUT_TRI_EN' in register 'TV_DATA_IO_TRI0_REG' (num_bits = 10)
WARNING:root:Could not interpret enumeratedValue '1': 'Disable' in field 'G_Y_CH_DATA_OUT_TRI_EN' in register 'TV_DATA_IO_TRI0_REG' (num_bits = 10)
WARNING:root:Could not interpret enumeratedValue '0': 'Enable' in field 'G_Y_CH_DATA_OUT_TRI_EN' in register 'TV_DATA_IO_TRI0_REG' (num_bits = 10)
WARNING:root:Could not interpret enumeratedValue '1': 'Disable' in field 'B_CR_CH_DATA_OUT_TRI_EN' in register 'TV_DATA_IO_TRI1_REG' (num_bits = 10)
WARNING:root:Could not interpret enumeratedValue '0': 'Enable' in field 'B_CR_CH_DATA_OUT_TRI_EN' in register 'TV_DATA_IO_TRI1_REG' (num_bits = 10)
WARNING:root:register 'TV_SAFE_PERIOD_REG' field 'SAFE_PERIOD_MODE' enum variants are not unique ([['000', ' unsafe '], ['001', ' safe '], ['010', ' safe at line_buf_curr_num > safe_period_fifo_num '], ['011', ' safe at 2 and safe at sync active '], ['100', ' safe at line   ']], counter = 2). Giving up.
WARNING:root:'TWI_ADDR': Invalid field ['For 7-bit addressing:', '', '', '']: Bitrange error
WARNING:root:'TWI_ADDR': Invalid field ['SLA6 – SLA0 is the 7-bit address of the TWI in slave mode. When the TWI receives this address after a START', '', '', '']: Bitrange error
WARNING:root:'TWI_ADDR': Invalid field ['condition, it will generate an interrupt and enter slave mode. (SLA6  corresponds to the first bit received', '', '', '']: Bitrange error
WARNING:root:'TWI_ADDR': Invalid field ['from the TWI bus.) If GCE is set to ‘1’, the TWI will also recognize the general call address (00h).', '', '', '']: Bitrange error
WARNING:root:'TWI_ADDR': Invalid field ['For 10-bit addressing:', '', '', '']: Bitrange error
WARNING:root:'TWI_ADDR': Invalid field ['When  the  address  received  starts  with b’11110,  the  TWI  recognizes b’11110  as  the  first  part  of  a 10-bit', '', '', '']: Bitrange error
WARNING:root:'TWI_ADDR': Invalid field ['address and if the next two bits match ADDR[2:1] (For example, SLAX9 and SLAX8 for the extended address', '', '', '']: Bitrange error
WARNING:root:'TWI_ADDR': Invalid field ['of the device), it sends an ACK. (The device does not generate an interrupt at this point.) If the next byte of', '', '', '']: Bitrange error
WARNING:root:'TWI_ADDR': Invalid field ['the address matches the XADDR register (SLAX7 – SLAX0), the TWI generates an interrupt and goes into slave', '', '', '']: Bitrange error
WARNING:root:'TWI_ADDR': Invalid field ['mode.', '', '', '']: Bitrange error
WARNING:root:Could not interpret enumeratedValue '000': 'OK' in field 'TRAN_RESULT' in register 'TWI_DRV_CTRL' (num_bits = 4)
WARNING:root:Could not interpret enumeratedValue '001': 'FAIL' in field 'TRAN_RESULT' in register 'TWI_DRV_CTRL' (num_bits = 4)
WARNING:root:register 'TWI_DRV_CTRL' field 'TWI_STA' enum variants are not unique ([('0x00', ' bus error '), ('0x08', ' START condition transmitted '), ('0x10', ' Repeated START condition transmitted '), ('0x18', ' Address + Write bit transmitted, ACK received '), ('0x20', ' Address + Write bit transmitted, ACK not received '), ('0x28', ' Data byte transmitted in master mode, ACK received '), ('0x30', ' Data byte transmitted in master mode, ACK not received '), ('0x38', ' Arbitration lost in address or data byte '), ('0x40', ' Address + Read bit transmitted, ACK received '), ('0x48', ' Address + Read bit transmitted, ACK not received '), ('0x50', ' Data byte received in master mode, ACK received '), ('0x58', ' Data byte received in master mode, ACK not received '), ('0x01', ' Timeout when sending the 9  SCL clock'), ('Other', ' Reserved ')], counter = 3). Giving up.
WARNING:root:'TWI_DRV_SLV': field 'CMD': Maybe parse error; description='R/W operation to slave device \n0: Write \n1: Read '
WARNING:root:register 'TWI_STAT' field 'STA' enum variants are not unique ([('0x00', ' Bus error '), ('0x08', ' START condition transmitted '), ('0x10', ' Repeated START condition transmitted '), ('0x18', ' Address + Write bit transmitted, ACK received '), ('0x20', ' Address + Write bit transmitted, ACK not received '), ('0x28', ' Data byte transmitted in master mode, ACK received '), ('0x30', ' Data byte transmitted in master mode, ACK not received '), ('0x38', ' Arbitration lost in address or data byte '), ('0x40', ' Address + Read bit transmitted, ACK received '), ('0x48', ' Address + Read bit transmitted, ACK not received '), ('0x50', ' Data byte received in master mode, ACK transmitted '), ('0x58', ' Data byte received in master mode, not ACK transmitted '), ('0x60', ' Slave address + Write bit received, ACK transmitted '), ('0x68', '  Arbitration  lost  in  the  address  as  master,  slave  address  +  Write bit received, ACK transmitted '), ('0x70', ' General Call address received, ACK transmitted '), ('0x78', '  Arbitration  lost  in  the  address  as  master,  General  Call  address received, ACK transmitted '), ('0x80', '  Data  byte  received  after  slave  address  received,  ACK  transmitted '), ('0x88', '  Data  byte  received  after  slave  address  received,  not  ACK  transmitted '), ('0x90', '  Data  byte  received  after  General  Call  received,  ACK  transmitted '), ('0x98', '  Data  byte  received  after  General  Call  received,  not  ACK  transmitted '), ('0xA0', ' STOP or repeated START condition received in slave mode '), ('0xA8', ' Slave address + Read bit received, ACK transmitted '), ('0xB0', '  Arbitration  lost  in  the  address  as  master,  slave  address  +  Read bit received, ACK transmitted '), ('0xB8', ' Data byte transmitted in slave mode, ACK received '), ('0xC0', ' Data byte transmitted in slave mode, ACK not received '), ('0xC8', ' The Last byte transmitted in slave mode, ACK received '), ('0xD0', ' Second Address byte + Write bit transmitted, ACK received '), ('0xD8', '  Second  Address  byte  +  Write  bit  transmitted,  ACK  not  received '), ('0xF8', ' No relevant status information, INT_FLAG=0'), ('Others', ' Reserved   ')], counter = 3). Giving up.
WARNING:root:'UART_RXDMA_CTRL': Field names are not unique: ['RXDMA', 'RXDMA', 'RXDMA', 'RXDMA', 'RXDMA', 'RXDMA']
INFO:root:[('UART0', '0x02500000 '), ('UART1', '0x02500400 '), ('UART2', '0x02500800 '), ('UART3', '0x02500C00 '), ('UART4', '0x02501000 '), ('UART5', '0x02501400   ')]: Automatically adding register 'UART_RXDMA_LMT' even though it's not mentioned in the summary (note: this is working around a bug in the PDF)
INFO:root:[('UART0', '0x02500000 '), ('UART1', '0x02500400 '), ('UART2', '0x02500800 '), ('UART3', '0x02500C00 '), ('UART4', '0x02501000 '), ('UART5', '0x02501400   ')]: Automatically adding register 'UART_RXDMA_IE' even though it's not mentioned in the summary (note: this is working around a bug in the PDF)
INFO:root:[('UART0', '0x02500000 '), ('UART1', '0x02500400 '), ('UART2', '0x02500800 '), ('UART3', '0x02500C00 '), ('UART4', '0x02501000 '), ('UART5', '0x02501400   ')]: Automatically adding register 'UART_RXDMA_IS' even though it's not mentioned in the summary (note: this is working around a bug in the PDF)
INFO:root:[('UART0', '0x02500000 '), ('UART1', '0x02500400 '), ('UART2', '0x02500800 '), ('UART3', '0x02500C00 '), ('UART4', '0x02501000 '), ('UART5', '0x02501400   ')]: Automatically adding register 'UART_RXDMA_SADDRH' even though it's not mentioned in the summary (note: this is working around a bug in the PDF)
INFO:root:[('UART0', '0x02500000 '), ('UART1', '0x02500400 '), ('UART2', '0x02500800 '), ('UART3', '0x02500C00 '), ('UART4', '0x02501000 '), ('UART5', '0x02501400   ')]: Automatically adding register 'UART_RXDMA_CTRL' even though it's not mentioned in the summary (note: this is working around a bug in the PDF)
INFO:root:[('UART0', '0x02500000 '), ('UART1', '0x02500400 '), ('UART2', '0x02500800 '), ('UART3', '0x02500C00 '), ('UART4', '0x02501000 '), ('UART5', '0x02501400   ')]: Automatically adding register 'UART_RXDMA_RADDRH' even though it's not mentioned in the summary (note: this is working around a bug in the PDF)
INFO:root:[('UART0', '0x02500000 '), ('UART1', '0x02500400 '), ('UART2', '0x02500800 '), ('UART3', '0x02500C00 '), ('UART4', '0x02501000 '), ('UART5', '0x02501400   ')]: Automatically adding register 'UART_RXDMA_WADDRH' even though it's not mentioned in the summary (note: this is working around a bug in the PDF)
INFO:root:[('UART0', '0x02500000 '), ('UART1', '0x02500400 '), ('UART2', '0x02500800 '), ('UART3', '0x02500C00 '), ('UART4', '0x02501000 '), ('UART5', '0x02501400   ')]: Automatically adding register 'UART_RXDMA_BL' even though it's not mentioned in the summary (note: this is working around a bug in the PDF)
INFO:root:[('UART0', '0x02500000 '), ('UART1', '0x02500400 '), ('UART2', '0x02500800 '), ('UART3', '0x02500C00 '), ('UART4', '0x02501000 '), ('UART5', '0x02501400   ')]: Automatically adding register 'UART_RXDMA_SADDRL' even though it's not mentioned in the summary (note: this is working around a bug in the PDF)
INFO:root:[('UART0', '0x02500000 '), ('UART1', '0x02500400 '), ('UART2', '0x02500800 '), ('UART3', '0x02500C00 '), ('UART4', '0x02501000 '), ('UART5', '0x02501400   ')]: Automatically adding register 'UART_RXDMA_DCNT' even though it's not mentioned in the summary (note: this is working around a bug in the PDF)
INFO:root:[('UART0', '0x02500000 '), ('UART1', '0x02500400 '), ('UART2', '0x02500800 '), ('UART3', '0x02500C00 '), ('UART4', '0x02501000 '), ('UART5', '0x02501400   ')]: Automatically adding register 'UART_RXDMA_RADDRL' even though it's not mentioned in the summary (note: this is working around a bug in the PDF)
INFO:root:[('UART0', '0x02500000 '), ('UART1', '0x02500400 '), ('UART2', '0x02500800 '), ('UART3', '0x02500C00 '), ('UART4', '0x02501000 '), ('UART5', '0x02501400   ')]: Automatically adding register 'UART_RXDMA_STR' even though it's not mentioned in the summary (note: this is working around a bug in the PDF)
INFO:root:[('UART0', '0x02500000 '), ('UART1', '0x02500400 '), ('UART2', '0x02500800 '), ('UART3', '0x02500C00 '), ('UART4', '0x02501000 '), ('UART5', '0x02501400   ')]: Automatically adding register 'UART_FCC' even though it's not mentioned in the summary (note: this is working around a bug in the PDF)
INFO:root:[('UART0', '0x02500000 '), ('UART1', '0x02500400 '), ('UART2', '0x02500800 '), ('UART3', '0x02500C00 '), ('UART4', '0x02501000 '), ('UART5', '0x02501400   ')]: Automatically adding register 'UART_RXDMA_WADDRL' even though it's not mentioned in the summary (note: this is working around a bug in the PDF)
INFO:root:[('UART0', '0x02500000 '), ('UART1', '0x02500400 '), ('UART2', '0x02500800 '), ('UART3', '0x02500C00 '), ('UART4', '0x02501000 '), ('UART5', '0x02501400   ')]: Automatically adding register 'UART_RXDMA_STA' even though it's not mentioned in the summary (note: this is working around a bug in the PDF)
WARNING:root:register 'UART_LCR' field 'EPS' enum variants are not unique ([('00', ' Odd Parity '), ('01', ' Even Parity'), ('1X', ' Reverse LCR[4]  In RS485 mode, it is the 9th bit--address bit. '), ('11', ' 9th bit = 0, indicates that this is a data byte. '), ('10', ' 9th bit = 1, indicates that this is an address byte. ')], counter = 3). Giving up.
WARNING:root:register 'UART_LCR' field 'EPS' enum variants are not unique ([('00', ' Odd Parity '), ('01', ' Even Parity'), ('1X', ' Reverse LCR[4]  In RS485 mode, it is the 9th bit--address bit. '), ('11', ' 9th bit = 0, indicates that this is a data byte. '), ('10', ' 9th bit = 1, indicates that this is an address byte. ')], counter = 3). Giving up.
WARNING:root:register 'UART_LCR' field 'EPS' enum variants are not unique ([('00', ' Odd Parity '), ('01', ' Even Parity'), ('1X', ' Reverse LCR[4]  In RS485 mode, it is the 9th bit--address bit. '), ('11', ' 9th bit = 0, indicates that this is a data byte. '), ('10', ' 9th bit = 1, indicates that this is an address byte. ')], counter = 3). Giving up.
WARNING:root:register 'UART_LCR' field 'EPS' enum variants are not unique ([('00', ' Odd Parity '), ('01', ' Even Parity'), ('1X', ' Reverse LCR[4]  In RS485 mode, it is the 9th bit--address bit. '), ('11', ' 9th bit = 0, indicates that this is a data byte. '), ('10', ' 9th bit = 1, indicates that this is an address byte. ')], counter = 3). Giving up.
WARNING:root:register 'UART_LCR' field 'EPS' enum variants are not unique ([('00', ' Odd Parity '), ('01', ' Even Parity'), ('1X', ' Reverse LCR[4]  In RS485 mode, it is the 9th bit--address bit. '), ('11', ' 9th bit = 0, indicates that this is a data byte. '), ('10', ' 9th bit = 1, indicates that this is an address byte. ')], counter = 3). Giving up.
WARNING:root:register 'UART_LCR' field 'EPS' enum variants are not unique ([('00', ' Odd Parity '), ('01', ' Even Parity'), ('1X', ' Reverse LCR[4]  In RS485 mode, it is the 9th bit--address bit. '), ('11', ' 9th bit = 0, indicates that this is a data byte. '), ('10', ' 9th bit = 1, indicates that this is an address byte. ')], counter = 3). Giving up.
svd2rust --target "riscv" -i phase3_host.svd
[INFO  svd2rust] Parsing device from SVD file
[INFO  svd2rust] Rendering device
[WARN  svd2rust::generate::peripheral] Found type name conflict with region Some("uart"), renamed to Some("uart_dll")
[WARN  svd2rust::generate::peripheral] Found type name conflict with region Some("uart"), renamed to Some("uart_dlh")
[WARN  svd2rust::generate::peripheral] Found type name conflict with region Some("uart"), renamed to Some("uart_fcr")
[WARN  svd2rust::generate::peripheral] Found type name conflict with region Some("uart"), renamed to Some("uart_dll")
[WARN  svd2rust::generate::peripheral] Found type name conflict with region Some("uart"), renamed to Some("uart_dlh")
[WARN  svd2rust::generate::peripheral] Found type name conflict with region Some("uart"), renamed to Some("uart_fcr")
[WARN  svd2rust::generate::peripheral] Found type name conflict with region Some("uart"), renamed to Some("uart_dll")
[WARN  svd2rust::generate::peripheral] Found type name conflict with region Some("uart"), renamed to Some("uart_dlh")
[WARN  svd2rust::generate::peripheral] Found type name conflict with region Some("uart"), renamed to Some("uart_fcr")
[WARN  svd2rust::generate::peripheral] Found type name conflict with region Some("uart"), renamed to Some("uart_dll")
[WARN  svd2rust::generate::peripheral] Found type name conflict with region Some("uart"), renamed to Some("uart_dlh")
[WARN  svd2rust::generate::peripheral] Found type name conflict with region Some("uart"), renamed to Some("uart_fcr")
[WARN  svd2rust::generate::peripheral] Found type name conflict with region Some("uart"), renamed to Some("uart_dll")
[WARN  svd2rust::generate::peripheral] Found type name conflict with region Some("uart"), renamed to Some("uart_dlh")
[WARN  svd2rust::generate::peripheral] Found type name conflict with region Some("uart"), renamed to Some("uart_fcr")
[WARN  svd2rust::generate::peripheral] Found type name conflict with region Some("uart"), renamed to Some("uart_dll")
[WARN  svd2rust::generate::peripheral] Found type name conflict with region Some("uart"), renamed to Some("uart_dlh")
[WARN  svd2rust::generate::peripheral] Found type name conflict with region Some("uart"), renamed to Some("uart_fcr")

daym / allwinner-register-interface-extractor

New version #4

References

1