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db-tu-dresden / TVLPrimitiveData

Template Vector Library Primitive Data
Apache License 2.0
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functor overloading #22

Open cmrschwarz opened 1 year ago

cmrschwarz commented 1 year ago

Currently, calls to overloaded primitives which happen to have functors with overlapping domains generate a compiler error, even if the conflicting implementation is only provided once.

Here an example where shift_left is overloaded for vector registers and for scalars, which causes an ambiguity for the scalar extension: https://github.com/db-tu-dresden/TVLPrimitiveData/tree/0014cc1c40f385d53e025cf4a9c1b3be1b67df06

The compiler error on gcc (Ubuntu 9.4.0-1ubuntu1~20.04.1) is as follows:


TVLGen/build/generator_output/src/test/unit_test.cpp: In instantiation of ‘bool tvl::test_shift_left_default() [with Vec = tvl::simd<unsigned int, tvl::scalar>]’:
TVLGen/build/generator_output/src/test/unit_test.cpp:1928:7:   required from here
TVLGen/build/generator_output/src/test/unit_test.cpp:268:48: error: call of overloaded ‘shift_left<tvl::simd<unsigned int, tvl::scalar, 32> >(unsigned int&, unsigned int&)’ is ambiguous
  268 |             storeu<Vec>(result, shift_left<Vec>(vec, shift));
      |                                 ~~~~~~~~~~~~~~~^~~~~~~~~~~~
In file included from TVLGen/build/generator_output/include/generated/tvl_generated.hpp:41,
                 from TVLGen/build/generator_output/include/tvlintrin.hpp:39,
                 from TVLGen/build/generator_output/src/test/unit_test.cpp:25:
TVLGen/build/generator_output/include/generated/declarations/binary.hpp:95:66: note: candidate: ‘typename Vec::register_type tvl::shift_left(typename Vec::register_type, unsigned int) [with Vec = tvl::simd<unsigned int, tvl::scalar>; Idof = tvl::workaround; typename Vec::register_type = unsigned int]’
   95 |       [[nodiscard]] TVL_FORCE_INLINE typename Vec::register_type shift_left(
      |                                                                  ^~~~~~~~~~
TVLGen/build/generator_output/include/generated/declarations/binary.hpp:158:66: note: candidate: ‘typename Vec::register_type tvl::shift_left(typename Vec::register_type, typename Vec::register_type) [with Vec = tvl::simd<unsigned int, tvl::scalar>; Idof = tvl::workaround; typename Vec::register_type = unsigned int]’
  158 |       [[nodiscard]] TVL_FORCE_INLINE typename Vec::register_type shift_left(
      |                                                                  ^~~~~~~~~~
JPietrzykTUD commented 1 year ago

Please see db-tu-dresden/TVLGen@6e42c4f and db-tu-dresden/TVLGen#14