Closed dd86k closed 6 years ago
int ebx, ecx; asm { mov EAX, 4; xor ECX, ECX; cpuid; mov ebx, EBX; mov ecx, ECX; } writefln("L1 Cache: %s", ((ebx >> 22) + 1) * (((ebx >> 12) & 0x3ff) + 1) * ((ebx & 0xfff) + 1) * (ecx + 1));
just a myself kinda note
Done Intel, doing AMD at the moment (very different!)
Done in commit f95f8e8
Caching was verified on my Intel Core i7-3770 and my AMD Ryzen 5 2400G
just a myself kinda note