Closed dd86k closed 3 years ago
...If possible. Some people may be confused that L3 cache is usually shared across all cores and the L1 and L2 amounts is for a single core.
Current pain being the fact that the type 3 indicates unified (instructions+data), not shared
Kind of waiting on #9 if this is possible.
Done in 64d9d30 and 3b8095d.
Incoming in v0.18.0.
...If possible. Some people may be confused that L3 cache is usually shared across all cores and the L1 and L2 amounts is for a single core.