Additional testing for verification

deadlyBuzz / STLAnalyser

STL Analyser code

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Open deadlyBuzz opened 10 years ago

deadlyBuzz commented 10 years ago

[ ] Need to test parametric access to variables. Is a L LW16 an access to a parameter? Is it an input/ output access only?
[x] Need to verify that access via DIW requires an additional delay when using indirect accessing. E.G DIW[AR1,P#0.0] - Is this a double delay?
[ ] Also need to test when a Data Block access is referenced, if the program can handle it... DB24.DBW12

deadlyBuzz commented 10 years ago

Also to be tested...

[ ] s7300_instruction_list contains to different instruction times for "A", one in P22 and another on P27. The context for P27s application is not clear so it is not certain which one is to be used where.

deadlyBuzz commented 10 years ago

[X] Need to verify that access via DIW requires an additional delay when using indirect accessing. E.G DIW[AR1,P#0.0] - Is this a double delay? - Encoded as a Double delay from the Database. If this is no longer required, the Delay for the DIW or the AIRI can be set to Zero in the Database.
[ ] PIW and associated Input reading has different delays depending on the distribution architecture of the I/O. Once testing is being performed, evaluate the delay compared with what would be associated with I/O Access. may be required to treat all I/O as Local. ref #9

deadlyBuzz commented 10 years ago

[ ] Have nowhere encountered parametric access FC1.BYTE6 outside DB updates DB5.DBB3 so this hasn't been included but should be tested.

deadlyBuzz commented 10 years ago

[ ] I think I know this one but Just to test as well that you cannot have a Block call loop. E.G FUNCTION FC 1 ... CALL FC 3 ( VAR1 := 5 VAR2 := 6 ); ... END FUNCTION

FUNCTION FC 3 ... CALL FC 1 ... END FUNCTION Cannot resolve. - FC 1 delays impact FC 3 delays which impact FC 1 delays etc.