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1 month ago deepin pr auto review
i915: Fix broken PCI IDs for Tiger Lake and Ryzen 7 4700G
git-svn-id: ffe668792ed300d6c2daa1f6eba2e0aa28d7ec6c@311788 91177308-0d34-0410-b5e6-96231b3b80d8
This should be the last update of MTL graphics. and this PR is to for graphics bugfix and feature enabling. and at the same time, we expected paving a good way to 15th and 16th graphics backporting.
local testing on Intel SDP MTL machine, works fine.
here are the commit lists from upstream and its kernel version:
final_deepin_graphics_commits.list 3a8ecd4c3ede,drm/i915/cx0: Add intel_cx0_get_owned_lane_mask(),2023-08-17 12:25:13,Gustavo Sousa gustavo.sousa@intel.com v6.7-rc1~8^2~21^2~211 0f5c2e5bd2fc,drm/i915: Simplify intel_cx0_program_phy_lane() with loop,2023-08-17 12:25:14,Gustavo Sousa gustavo.sousa@intel.com v6.7-rc1~8^2~21^2~210 226fa3ab8be5,drm/i915/cx0: Program vswing only for owned lanes,2023-08-17 12:25:15,Gustavo Sousa gustavo.sousa@intel.com v6.7-rc1~8^2~21^2~208 fd279d21edd2,drm/i915/dp_mst: Use output_format to get the final link bpp,2023-08-18 09:42:15,Ankit Nautiyal ankit.k.nautiyal@intel.com v6.7-rc1~8^2~21^2~201 ae3a70adc273,drm/i915/regs: split out intel_color_regs.h,2023-08-25 13:12:10,Jani Nikula jani.nikula@intel.com v6.7-rc1~8^2~21^2~166 7f52ca642f80,drm/i915/color: move CHV CGM pipe mode read to intel_color,2023-08-25 13:12:17,Jani Nikula jani.nikula@intel.com v6.7-rc1~8^2~21^2~165 efe6fcb2dc27,drm/i915: move HSW+ gamma mode read to intel_color,2023-08-25 13:12:21,Jani Nikula jani.nikula@intel.com v6.7-rc1~8^2~21^2~164 cecdea151e78,drm/i915: move ILK+ CSC mode read to intel_color,2023-08-25 13:12:24,Jani Nikula jani.nikula@intel.com v6.7-rc1~8^2~21^2~163 f56e23edb196,drm/i915/color: move SKL+ gamma and CSC enable read to intel_color,2023-08-25 13:12:27,Jani Nikula jani.nikula@intel.com v6.7-rc1~8^2~21^2~162 9af09dfcdfa1,drm/i915/color: move pre-SKL gamma and CSC enable read to intel_color,2023-08-25 13:12:31,Jani Nikula jani.nikula@intel.com v6.7-rc1~8^2~21^2~161 51152acfdcb1,drm/i915/hdcp: Use intel_connector argument in intel_hdcp_shim,2023-08-29 13:51:39,Suraj Kandpal suraj.kandpal@intel.com v6.7-rc1~8^2~21^2~160 c1464a89e1a4,drm/i915: add minimal i915_gem_object_frontbuffer.h,2023-08-31 18:41:34,Jani Nikula jani.nikula@intel.com v6.7-rc1~8^2~21^2~144 113cdddcded6,drm/cec: add drm_dp_cec_attach() as the non-edid version of set edid,2023-09-01 11:47:53,Jani Nikula jani.nikula@intel.com v6.7-rc1~8^2~21^2~138 7218779efc46,drm/edid: add drm_edid_is_digital(),2023-09-01 11:47:53,Jani Nikula jani.nikula@intel.com v6.7-rc1~8^2~21^2~141 82b599ece3b8,drm/edid: parse source physical address,2023-09-01 11:47:53,Jani Nikula jani.nikula@intel.com v6.7-rc1~8^2~21^2~139 e1039cde6849,drm/i915/display: use drm_edid_is_digital(),2023-09-01 11:47:53,Jani Nikula jani.nikula@intel.com v6.7-rc1~8^2~21^2~140 130849f8ec14,drm/i915/hdcp: Use intel_connector as argument for hdcp_2_2_capable,2023-09-01 13:17:44,Suraj Kandpal suraj.kandpal@intel.com v6.7-rc1~8^2~21^2~143 9055e73e8e6a,drm/i915/dsb: Dump the DSB command buffer when DSB fails,2023-09-07 15:43:29,Ville Syrjälä ville.syrjala@linux.intel.com v6.7-rc1~8^2~21^2~115 088ca02108fc,drm/i915/dsb: Avoid corrupting the first register write,2023-09-07 15:44:16,Ville Syrjälä ville.syrjala@linux.intel.com v6.7-rc1~8^2~21^2~114 231b1d6c9ab6,drm/i915/dsb: Don't use indexed writes when byte enables are not all set,2023-09-07 15:44:41,Ville Syrjälä ville.syrjala@linux.intel.com v6.7-rc1~8^2~21^2~113 30b98ecbfbd6,drm/i915: Call the DDC bus i2c adapter "ddc",2023-09-15 14:47:09,Ville Syrjälä ville.syrjala@linux.intel.com v6.7-rc1~8^2~21^2~87 e046d1562491,drm/i915/hdmi: Use connector->ddc everwhere,2023-09-15 14:48:49,Ville Syrjälä ville.syrjala@linux.intel.com v6.7-rc1~8^2~21^2~81 ac6dcb63f244,drm/i915/hdmi: Nuke hdmi->ddc_bus,2023-09-15 14:49:10,Ville Syrjälä ville.syrjala@linux.intel.com v6.7-rc1~8^2~21^2~80 31a657528976,drm/i915/hdmi: Remove old i2c symlink,2023-09-15 14:50:04,Ville Syrjälä ville.syrjala@linux.intel.com v6.7-rc1~8^2~21^2~79 6686c30e455c,drm/i915: move more of the display probe to display code,2023-09-15 18:29:05,Jani Nikula jani.nikula@intel.com v6.7-rc1~8^2~21^2~74 f895e3db65a4,drm/i915: Move psr unlock out from the pipe update critical section,2023-09-20 22:27:08,Ville Syrjälä ville.syrjala@linux.intel.com v6.7-rc1~8^2~21^2~67 b4ac591b8e1b,drm/i915: Optimize out redundant M/N updates,2023-09-20 22:29:43,Ville Syrjälä ville.syrjala@linux.intel.com v6.7-rc1~8^2~21^2~62 f0f7ec743d06,drm/i915: Relocate is_in_vrr_range(),2023-09-20 22:30:08,Ville Syrjälä ville.syrjala@linux.intel.com v6.7-rc1~8^2~21^2~61 6a38b36c274f,drm/i915: Validate that the timings are within the VRR range,2023-09-20 22:30:55,Ville Syrjälä ville.syrjala@linux.intel.com v6.7-rc1~8^2~21^2~60 8f782270cc14,drm/i915: Disable VRR during seamless M/N changes,2023-09-20 22:31:21,Ville Syrjälä ville.syrjala@linux.intel.com v6.7-rc1~8^2~21^2~59 0ce013a4e840,drm/i915: Update VRR parameters in fastset,2023-09-20 22:31:39,Ville Syrjälä ville.syrjala@linux.intel.com v6.7-rc1~8^2~21^2~58 26f03ef81663,drm/i915: Assert that VRR is off during vblank evasion if necessary,2023-09-20 22:32:22,Ville Syrjälä ville.syrjala@linux.intel.com v6.7-rc1~8^2~21^2~57 16a9359401ed,drm/i915: Implement transcoder LRR for TGL+,2023-09-20 22:32:55,Ville Syrjälä ville.syrjala@linux.intel.com v6.7-rc1~8^2~21^2~56 8dde2e68a555,drm/i915: Re-order if/else ladder in intel_detect_pch(),2023-09-21 07:39:48,Lucas De Marchi lucas.demarchi@intel.com v6.7-rc1~8^2~21^2~49 65578d0d10d8,drm/i915/xe2lpd: Add fake PCH,2023-09-21 07:39:49,Gustavo Sousa gustavo.sousa@intel.com v6.7-rc1~8^2~21^2~48 cfeff354f70b,drm/i915/xe2lpd: Treat cursor plane as regular plane for DDB allocation,2023-09-21 07:39:50,Stanislav Lisovskiy stanislav.lisovskiy@intel.com v6.7-rc1~8^2~21^2~47 6f35a04fd663,drm/i915/xe2lpd: Read pin assignment from IOM,2023-09-21 08:18:06,Luca Coelho luciano.coelho@intel.com v6.7-rc1~8^2~21^2~40 9d404dad0bf8,drm/i915/lnl: Add gmbus/ddc support,2023-09-21 08:18:06,Lucas De Marchi lucas.demarchi@intel.com v6.7-rc1~8^2~21^2~36 696c331990cf,drm/i915/xe2lpd: Add support for HPD,2023-09-21 08:18:06,Gustavo Sousa gustavo.sousa@intel.com v6.7-rc1~8^2~21^2~38 fa1b97f85d3b,drm/i915/dsb: Use non-locked register access,2023-09-27 18:35:29,Ville Syrjälä ville.syrjala@linux.intel.com v6.7-rc1~8^2~21^2~25 357832b5cc04,drm/i915/dsb: Define more DSB bits,2023-09-27 18:36:19,Ville Syrjälä ville.syrjala@linux.intel.com v6.7-rc1~8^2~21^2~24 0c1c7a649975,drm/i915/dsb: Define the contents of some intstructions bit better,2023-09-27 18:38:17,Ville Syrjälä ville.syrjala@linux.intel.com v6.7-rc1~8^2~21^2~23 df3b91928698,drm/i915/dsb: Introduce intel_dsb_noop(),2023-09-27 18:38:40,Ville Syrjälä ville.syrjala@linux.intel.com v6.7-rc1~8^2~21^2~22 e39845d65179,drm/i915/dsb: Introduce intel_dsb_reg_write_masked(),2023-09-27 18:38:53,Ville Syrjälä ville.syrjala@linux.intel.com v6.7-rc1~8^2~21^2~21 5053121b25bf,drm/i915/dsb: Add support for non-posted DSB registers writes,2023-09-27 18:39:26,Ville Syrjälä ville.syrjala@linux.intel.com v6.7-rc1~8^2~21^2~20 5ae0da3fc78d,drm/i915/dsb: Load LUTs using the DSB during vblank,2023-09-27 18:40:58,Ville Syrjälä ville.syrjala@linux.intel.com v6.7-rc1~8^2~21^2~18 7678e089bd18,drm/i915/dsb: Evade transcoder undelayed vblank when using DSB,2023-09-27 18:46:08,Ville Syrjälä ville.syrjala@linux.intel.com v6.7-rc1~8^2~21^2~16 b4283282c953,drm/i915: Introduce skl_watermark_max_latency(),2023-09-27 18:46:22,Ville Syrjälä ville.syrjala@linux.intel.com v6.7-rc1~8^2~21^2~15 77d8285683d8,drm/i915: Introduce intel_crtc_scanline_to_hw(),2023-09-27 18:47:08,Ville Syrjälä ville.syrjala@linux.intel.com v6.7-rc1~8^2~21^2~14 f83b94d23770,drm/i915/dsb: Use DEwake to combat PkgC latency,2023-09-27 18:49:06,Ville Syrjälä ville.syrjala@linux.intel.com v6.7-rc1~8^2~21^2~13 fa7a7a1c9c05,drm/i915: Add helper to modeset a set of pipes,2023-09-28 12:52:15,Imre Deak imre.deak@intel.com v6.7-rc1~8^2~21^2~7 e3b269049103,drm/i915: Rename intel_modeset_all_pipes() to intel_modeset_all_pipes_late(),2023-09-28 12:52:17,Imre Deak imre.deak@intel.com v6.7-rc1~8^2~21^2~6 1050e4c2368e,drm/i915: Factor out a helper to check/compute all the CRTC states,2023-09-28 12:52:19,Imre Deak imre.deak@intel.com v6.7-rc1~8^2~21^2~5 5ed8c7bcf9a5,drm/i915/mocs: use to_gt() instead of direct &i915->gt,2023-10-04 18:27:33,Jani Nikula jani.nikula@intel.com v6.7-rc1~8^2~19^2~48 c788479a7c5b,drm/i915: Constify the snps/c10x PLL state checkers,2023-10-07 00:12:46,Ville Syrjälä ville.syrjala@linux.intel.com v6.7-rc1~8^2~19^2~29 bcdcae632740,drm/i915/dsb: Allocate command buffer from local memory,2023-10-13 16:24:34,Ville Syrjälä ville.syrjala@linux.intel.com v6.7-rc1~8^2~15^2~25 631b117ea8c3,drm/i915/dsb: Correct DSB command buffer cache coherency settings,2023-10-13 16:25:30,Ville Syrjälä ville.syrjala@linux.intel.com v6.7-rc1~8^2~15^2~24 b662c19654ca,drm/i915/display: Reset message bus after each read/write operation,2023-10-26 17:48:14,Mika Kahola mika.kahola@intel.com v6.8-rc1~21^2~27^2~150 b0462e94c964,drm/i915: Move the g45 PEG band gap HPD workaround to the HPD code,2023-10-31 08:31:00,Ville Syrjälä ville.syrjala@linux.intel.com v6.8-rc1~21^2~27^2~136 98ed369800f7,drm/i915/dsb: DSB code refactoring,2023-11-16 15:56:53,Animesh Manna animesh.manna@intel.com v6.8-rc1~21^2~27^2~55 9d6953335284,drm/i915: move _crtc_clock_get() to intel_dpll.c,2023-11-17 14:59:47,Jani Nikula jani.nikula@intel.com v6.8-rc1~21^2~27^2~53 b1f5279b5981,drm/i915/psr: Move plane sel fetch configuration into plane source files,2023-11-27 07:36:25,Jouni Högander jouni.hogander@intel.com v6.8-rc1~21^2~24^2~31 562f33836f51,drm/i915/dgfx: DGFX uses direct VBT pin mapping,2023-11-29 14:49:29,Clint Taylor clinton.a.taylor@intel.com v6.8-rc1~21^2~24^2~20 ef32c3cc9c62,drm/i915: correct the input parameter on _intel_dsb_commit(),2023-11-29 19:26:05,heminhong heminhong@kylinos.cn v6.8-rc1~21^2~24^2~22 6128becaeafa,drm/i915: Stop accessing crtc->state from the flip done irq,2023-12-09 04:13:57,Ville Syrjälä ville.syrjala@linux.intel.com v6.8-rc1~21^2~14^2~20 bac2d7d8e64b,drm/i915/display: Take care of VSC select field in video dip ctl register,2023-12-22 08:15:20,Jouni Högander jouni.hogander@intel.com v6.9-rc1~26^2~25^2~95 93cbc1accbce,drm/i915/mtl: Add fake PCH for Meteor Lake,2024-01-03 09:17:00,Haridhar Kalvala haridhar.kalvala@intel.com v6.9-rc1~26^2~25^2~93 c27f010aa188,drm/i915: Disable DSB in Xe KMD,2024-01-05 06:33:31,José Roberto de Souza jose.souza@intel.com v6.9-rc1~26^2~25^2~82 bddacdf4861c,drm/i915: Add additional ARL PCI IDs,2024-01-18 15:24:32,Matt Roper matthew.d.roper@intel.com v6.9-rc1~26^2~25^2~44 84bf82f4f866,drm/i915/xelpg: Extend driver code of Xe_LPG to Xe_LPG+,2024-01-18 15:28:40,Harish Chegondi harish.chegondi@intel.com v6.9-rc1~26^2~15^2~9 c045bc428f77,drm/i915: Decouple intel_crtc_vblank_evade_scanlines() from atomic commits,2024-01-22 19:02:58,Ville Syrjälä ville.syrjala@linux.intel.com v6.9-rc1~26^2~25^2~41 bb83f348ead2,drm/i915: Reorder drm_vblank_put() vs. need_vlv_dsi_wa,2024-01-22 19:03:11,Ville Syrjälä ville.syrjala@linux.intel.com v6.9-rc1~26^2~25^2~40 637bda52bf36,drm/i915: Introduce struct intel_vblank_evade_ctx,2024-01-22 19:03:21,Ville Syrjälä ville.syrjala@linux.intel.com v6.9-rc1~26^2~25^2~39 b1f9bc3dbe28,drm/i915: Include need_vlv_dsi_wa in intel_vblank_evade_ctx,2024-01-22 19:03:32,Ville Syrjälä ville.syrjala@linux.intel.com v6.9-rc1~26^2~25^2~38 b5ad7ce024b3,drm/i915: Extract intel_vblank_evade(),2024-01-22 19:03:40,Ville Syrjälä ville.syrjala@linux.intel.com v6.9-rc1~26^2~25^2~37 318ec320c6c7,drm/i915: Move the min/max scanline sanity check into intel_vblank_evade(),2024-01-22 19:04:03,Ville Syrjälä ville.syrjala@linux.intel.com v6.9-rc1~26^2~25^2~36 1de63528e728,drm/i915: Perform vblank evasion around legacy cursor updates,2024-01-22 19:04:51,Ville Syrjälä ville.syrjala@linux.intel.com v6.9-rc1~26^2~25^2~34 6bc41f9cf252,Revert "drm/i915/xe2lpd: Treat cursor plane as regular plane for DDB allocation",2024-01-22 19:05:48,Ville Syrjälä ville.syrjala@linux.intel.com v6.9-rc1~26^2~25^2~33 6d46d09a0d7d,drm/i915/mtl: Wake GT before sending H2G message,2024-01-23 16:57:47,Vinay Belgaumkar vinay.belgaumkar@intel.com v6.9-rc1~26^2~15^2~7 d5c7854b50e6,drm/i915/xe2lpd: Move D2D enable/disable,2024-01-30 07:20:21,Lucas De Marchi lucas.demarchi@intel.com v6.9-rc1~26^2~25^2~28 82195d48b77c,drm/print: move enum drm_debug_category etc. earlier in drm_print.h,2024-02-09 11:51:49,Jani Nikula jani.nikula@intel.com v6.9-rc1~26^2~23^2~38 dea1731dfc25,drm/i915: Move intel_vblank_evade() & co. into intel_vblank.c,2024-01-22 19:04:13,Ville Syrjälä ville.syrjala@linux.intel.com v6.9-rc1~26^2~25^2~35 d9b904d2efdf,drm/i915/display: update pll values in sync with Bspec for MTL,2024-02-14 09:27:25,Ravi Kumar Vodapalli ravi.kumar.vodapalli@intel.com v6.9-rc1~26^2~16^2~70 3d890f328773,drm/i915/lnl: Add pkgc related register,2024-02-23 11:50:46,Suraj Kandpal suraj.kandpal@intel.com v6.9-rc1~26^2~16^2~37 810e4519a1b3,drm/i915/vrr: Generate VRR "safe window" for DSB,2024-03-07 18:14:37,Ville Syrjälä ville.syrjala@linux.intel.com v6.10-rc1~15^2~26^2~187 65ea19a698f2,drm/i915/hdmi: convert _port_to_ddc_pin() to *_encoder_to_ddc_pin(),2024-03-21 14:09:58,Jani Nikula jani.nikula@intel.com v6.10-rc1~15^2~26^2~126 caf3d748f646,drm/i915/dp: Remove support for UHBR13.5,2024-04-02 10:22:42,Arun R Murthy arun.r.murthy@intel.com v6.9-rc3~25^2^2~10