Finishing verilog code gen

[dgrnbrg]

Besides the obvious (implement the remainder of the functions and immediates), there are several parts that still need to be written:

1) Module-level code generation: easy

2) Better lookup: the name-table is currently a map from piplin ast frags to their names in the generated verilog. This breaks down in a two places I've noticed: :noops (like trace & uninst), and :ports (since they must be pre-initialized but we don't cache their astfrags anywhere). :noops can be handled by a pass that elides them (which feels like the correct solution). :ports could be handled by including them in the module object, rather than just making them available in the (let...) in the (module...) macro.

[dgrnbrg]

I actually think that the name table needs a special lookup function that understands when a pipinst is passed in it must be converted to the verilog-repr, and when a port is passed in, it must be converted to the plain name of that port, and throws an exception when the lookup fails (current it returns nil, which causes data to be missing from the verilog output rather than just failing w/ an error.

[dgrnbrg]

Ops needing codegen: <, >, <=, >=, not, -, *, bit-and, bit-or, bit-xor, deserialize, and bit-not (which doesn't exist anywhere).

Also need to generate containing module.

[dgrnbrg]

This is done (except bit-not, which doesn't exist at all yet)