dgrnbrg
commented
12 years ago I now have only :make-array, :array-assoc, and :array-get.
I now realize that arrays correspond to verilog memories, which must be put into a register type, because non-constant gets will not work on verilog vectors.
To accomplish this, outputs which are arrays must be treated differently in synthesis. They will be created as memories in verilog.
To allow (assoc ...) to be used in simulation (but not synthesis), it will remain, without the ability to generate verilog.
We will add an additional valid kind of register, which is a dynamic index array assignment register. This will be used like: (connect (get my-array index-expr) (calculate...))
To synthesize this, we'll just need to alter the code generation on line 492 to return either the reg's name or "name[index-expr]". This will probably require deferring that name generation until after the name-table is computed. The declarations will also need to change for arrays.
To simulate this, we'll need to modify make-connection. It will need to check if the reg is an :array-get ast node, and if it is, it will have to also make the index-fn as well as the sim-fn, and it will have to get the array port and do the assoc in the make-connection.
:make-array and :array-assoc are the only operations needed at the moment.
A kind of :array-get based on nth also needs to be written.