I wasn't sure how else to communicate with you, as I couldn't find an email address.
Have you seen the project fpgalink. It has utitlies and drivers for easily communicating with many different boards so that the same code can be used for many different setups.
http://www.makestuff.eu/wordpress/software/fpgalink/
They have support for eight or so boards. There have been some efforts to integrate it with Myhdl - to have a high language way of writing hdl, programming fpga's, and interacting with the board from the host. However, you project is much more extensible and natural.
The creator also has a python utility hdlmake.py that generates bit files from verilog and vhdl files. This negates that need to open ISE. ISE and altera are accessed through command line utilities.
https://github.com/makestuff/hdlmake
I'd be happy to help you integrate the projects. I think this would make a complete workflow for developing fpga's.
fitzsnaggle@gmail.com
I wasn't sure how else to communicate with you, as I couldn't find an email address.
Have you seen the project fpgalink. It has utitlies and drivers for easily communicating with many different boards so that the same code can be used for many different setups. http://www.makestuff.eu/wordpress/software/fpgalink/
It has some preliminary java bindings : https://groups.google.com/forum/#!topic/fpgalink-users/UmyAgiapWLc
They have support for eight or so boards. There have been some efforts to integrate it with Myhdl - to have a high language way of writing hdl, programming fpga's, and interacting with the board from the host. However, you project is much more extensible and natural.
The creator also has a python utility hdlmake.py that generates bit files from verilog and vhdl files. This negates that need to open ISE. ISE and altera are accessed through command line utilities. https://github.com/makestuff/hdlmake
I'd be happy to help you integrate the projects. I think this would make a complete workflow for developing fpga's. fitzsnaggle@gmail.com