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dgschwend / zynqnet

Master Thesis "ZynqNet: An FPGA-Accelerated Embedded Convolutional Neural Network"
GNU General Public License v3.0
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zynqnet on xilinx XC7Z020 #29

Open ortalik opened 6 years ago

ortalik commented 6 years ago

Hello David,

I am interested in testing your network on the XC7Z020 SoC which is smaller than the XC7Z045 you were using. I can see that the main issue is with the bram utilization. Do you have an idea how this could work? Are there any changes we could try? Or do we need to completely redesign?

Edit: we have already tried to cut the number of processing elements. Even with 1 there is over utilization. We can see that most BRAMs were used by WeightsCache.WBRAM.

Thank you!

mslavescu commented 6 years ago

I'm also interested in a variant of this network for PYNQ-Z1 board, that uses ZYNQ XC7Z020-1CLG400C: https://store.digilentinc.com/pynq-z1-python-productivity-for-zynq/

ysdagar commented 6 years ago

I'm also interested in a variant of this network for Xilinx-ZC702 Evaluation Kit that uses ZYNQ XC7Z020 Soc.

JohnnyOpcode commented 6 years ago

I'm fascinated by the people who want this on a Z7020. I guess they can't comprehend the FPGA resources required for this magnificent piece of engineering. I guess they also can't try and optimize the code further and expect someone (the author) to do it for them. My suggestion would be to study this work of art, learn and stand on the shoulders of greats like dgschwend. I dare you all to do better.

ysdagar commented 6 years ago

Thank you Johnyopcode, for your encouraging words & yes challenge taken! :) :)