Open wangj346 opened 6 years ago
I am Bhagavan , from chennai, Tamil Nadu, India
what are all the platforms you used for Synthesis the Zyngnet code.
1) Windows or Linux 2) vivado HLS version
Because I faced lot of errors. I used Windows 10 vivado HLS 2018.3
Please help me .
I am Bhagavan , from chennai, Tamil Nadu, India
what are all the platforms you used for Synthesis the Zyngnet code.
- Windows or Linux
- vivado HLS version
Because I faced lot of errors. I used Windows 10 vivado HLS 2018.3
Please help me .
hi,i have the same question with you. have you solved them?
I am sorry to reply you late. I roughly remember that I use vivado HLS to create an IP core and than employ it to block design tools in vivado. 发送自 Windows 10 版邮件https://go.microsoft.com/fwlink/?LinkId=550986应用
发件人: ihaterecursionmailto:notifications@github.com 发送时间: 2021年1月8日 20:47 收件人: dgschwend/zynqnetmailto:zynqnet@noreply.github.com 抄送: wangj346mailto:w280400191@hotmail.com; Authormailto:author@noreply.github.com 主题: Re: [dgschwend/zynqnet] How to run the project on FPGA? (#46)
I am Bhagavan , from chennai, Tamil Nadu, India
what are all the platforms you used for Synthesis the Zyngnet code.
Because I faced lot of errors. I used Windows 10 vivado HLS 2018.3
Please help me .
hi,i have the same question with you. have you solved them?
― You are receiving this because you authored the thread. Reply to this email directly, view it on GitHubhttps://github.com/dgschwend/zynqnet/issues/46#issuecomment-756738133, or unsubscribehttps://github.com/notifications/unsubscribe-auth/AG44NGAMPQ6CPTYY2R3SJWTSY35FBANCNFSM4E6Y3LQQ.
Hi dgschwend, thanks for your sharing. I am interested in the project and try to run it on Xilinx ZC706. I have successfully run the HLS synthesis and create the bitstream. Then I make the Makefile in the folder‘_FIRMWARE’ and create the test.exe. It run perfectly in the PC Linux with ./test CPU indata.bin. Then I modefiy the IP core according to the ZC706 and create the bitstream successfully. However when I copy all the files and my bitstream to the Linux of the ZC706, and run the ./test FPGA indata.bin. The ZC706 stuck and I have to reboot it. May I ask how do you run the project on FPGA ?(SDSoc or SDK or else) and any suggestions about the problem.