about alexnet

[OverDriveMC]

Hello, I try to use python to run the Alexnet model,My code like this:

import caffe
MODEL_FILE = 'alexnet_four_channel_model.caffemodel'
DEPLOY_FILE = 'config/deploy.prototxt'
TEST_ROOT = 'datas/'

caffe.set_mode_cpu()
net = caffe.Net(DEPLOY_FILE, MODEL_FILE, caffe.TEST)

transformer = caffe.io.Transformer({'data': net.blobs['data'].data.shape})
transformer.set_transpose('data', (2, 0, 1))
transformer.set_raw_scale('data', 255)
transformer.set_channel_swap('data', (2, 1, 0))
net.blobs['data'].reshape(1, 3, 227, 227)

img = caffe.io.load_image('temp.jpg')

net.blobs['data'].data[...] = transformer.preprocess('data', img)

out = net.forward()
pridects = out['prob']
predict = pridects.argmax()
print(predict)

Then, I found the deploy.protxt doesn't have an softmax layer, and I found that the the first dim of inputshape must be 256? does it mean the number of pictures? I try to modify it to 1, then it signals an error that ` CHECK(num % 16 == 0); ` I want to know what I need to do so that I can run the fpga_alexnet model. Now, I have compiled an crp_layer_hwcn_cpfp.xclbin file, and put it into the folder .build_release/opencl/src/caffe/layers/, what others I should do?

Thanks~

[dicecco1]

Yeah I should probably document that a little more clearly, the batch size should be a multiple of 16, preferably something larger e.g. 64-256 to avoid loop carry dependencies. If it gives you an error related to the batch size, then just crank it up to be higher.

The last layer of the deploy.prototxt file is softmax.

[dicecco1]

Some other notes: performance isn't too great on the FC layers, and some layers run on the CPU in fp32 (softmax, lrn layers in particular for this model).

[dicecco1]

Also, in general I've been running using the caffe executable directly rather than python interfaces. I think the python interfaces should work as well but I haven't tested them extensively.

[OverDriveMC]

Can I apply this project to xilinx virtex450t?

[dicecco1]

Is there SDAccel support for the virtex450t? I mean you could technically use the kernels directly since they're written in HLS, but the framework uses OpenCL for the CPU-FPGA transfers so if there's no SDAccel support you'd have to rewrite the host side of things.