search

dillonhuff / clockwork

A polyhedral compiler for hardware accelerators
56 stars 12 forks source link

CoreIR Codegen for Port Bundle #22

Closed joyliu37 closed 4 years ago

joyliu37 commented 4 years ago

I found in the current CodeGen you are using a flatten long width bit interface. In order to wire the bundle with correct port, I need to slice or concat. I just quick chat with Ross about the port bundle interface. He suggest to use an array of 16bit interface. And that's the formal format for them to do PnR. And it will be easier to sel the port inside a wide bundle. Is these reasonable to you? If so I could do a quick change in the global codegen and make a PR.

dillonhuff commented 4 years ago

@joyliu37 sure thats fine.

dillonhuff commented 4 years ago

Also this might be relevant for @jeffsetter since he is generating the compute units for the applications.

jeffsetter commented 4 years ago

Sounds good to me. However, I believe we have had trouble with CoreIR simulating hierarchical interfaces in the past.

dillonhuff commented 4 years ago

@joyliu37 can we close this issue now?