Quartus Prime 18.1 qsys issue

dimag0g / nios_duino

NIOSDuino - Arduino framework running on NIOS II

GNU Lesser General Public License v2.1

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Quartus Prime 18.1 qsys issue #12

Closed richard-445 closed 7 months ago

richard-445 commented 3 years ago

This model of Quartus Prime doesn't recognize your pwm_0 input from the qsys file you had provided. Was this component in the processor just a" PIO Intel FPGA IP" output setup for outputting a PWM signal?

dimag0g commented 3 years ago

Hi Richard. Could you explain what is meant by "input"? The verilog file, the TCL file (and which one) or something else. Could you post the exact error message or a screenshot?

Reminder: the PWM component has to be installed separately from https://github.com/dimag0g/avalon_pwm