Closed richard-445 closed 7 months ago
Hi Richard. Could you explain what is meant by "input"? The verilog file, the TCL file (and which one) or something else. Could you post the exact error message or a screenshot?
Reminder: the PWM component has to be installed separately from https://github.com/dimag0g/avalon_pwm
This model of Quartus Prime doesn't recognize your pwm_0 input from the qsys file you had provided. Was this component in the processor just a" PIO Intel FPGA IP" output setup for outputting a PWM signal?