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dineshannayya / riscduino

Arduino compatible Risc-V Based SOC
Apache License 2.0
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question about clock skew adjust #14

Closed clp510 closed 2 years ago

clp510 commented 2 years ago

In your design I have seen a lot of clock skew adjust logic, why clock skew adjust is necessary ?

dineshannayya commented 2 years ago

When two macro interact each other in same clock domain. To met timing closure we need to match the clock latency between these macro. Typically in commercial tool will have option to define clock latency to be achieved during macro hardening. These feature is not available in openlane, So we are adding clock skew adjust logic to each entry point of clock tree of the macro. During the Top-level timing analysis we will adjust each the macro clock skew inside each macro to achieve clean timing closure. All clock skew adjust delay are controlled by register inside the wb_host block.

clp510 commented 2 years ago

I see, thanks a lot.