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dineshannayya / riscduino

Arduino compatible Risc-V Based SOC
Apache License 2.0
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PDN probelm #16

Closed pengpeng-lian closed 2 years ago

pengpeng-lian commented 2 years ago

I have now put all the Verilogs together to run a macro, but have encountered a problem, reporting the following error #############ERROR############################### [STEP 6] [INFO]: Running Tap/Decap Insertion... [INFO]: Connecting Power: vccd1 & vssd1 to All internal macros. [INFO]: Generating PDN... [ERROR]: PDN generation failed. [ERROR]: You may need to adjust your macro placements or PDN offsets/pitches to power all standard cell rails (or other PDN stripes) in your design. [INFO]: Generating final set of reports... [INFO]: Created manufacturability report at 'user_project_wrapper/runs/user_project_wrapper/reports/manufacturability.rpt'. [INFO]: Created metrics report at 'user_project_wrapper/runs/user_project_wrapper/reports/metrics.csv'. [INFO]: Saving runtime environment... [ERROR]: Flow failed.

#########################config.tcl############################################### set ::env(PDK) "sky130A" set ::env(STD_CELL_LIBRARY) "sky130_fd_sc_hd"

YOU ARE NOT ALLOWED TO CHANGE ANY VARIABLES DEFINED IN THE FIXED WRAPPER CFGS

source $::env(CARAVEL_ROOT)/openlane/user_project_wrapper/fixed_wrapper_cfgs.tcl

YOU CAN CHANGE ANY VARIABLES DEFINED IN THE DEFAULT WRAPPER CFGS BY OVERRIDING THEM IN THIS CONFIG.TCL

source $::env(CARAVEL_ROOT)/openlane/user_project_wrapper/default_wrapper_cfgs.tcl

set script_dir [file dirname [file normalize [info script]]] set proj_dir [file dirname [file normalize [info script]]]

set ::env(ROUTING_CORES) "6"

set ::env(DESIGN_NAME) user_project_wrapper set verilog_root $proj_dir/../../verilog/

User Configurations

# set ::env(DESIGN_IS_CORE) 1 set ::env(FP_PDN_CORE_RING) 1

Source Verilog Files

set ::env(VERILOG_FILES) "\ $proj_dir/../../verilog/rtl//yifive/ycr1c/src/top/ycr_top_wb.sv \ $proj_dir/../../verilog/rtl/user_project_wrapper.v \ $script_dir/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv \ $script_dir/../../verilog/rtl/pinmux/src/pinmux.sv \ $script_dir/../../verilog/rtl/pinmux/src/pinmux_reg.sv \ $script_dir/../../verilog/rtl/pinmux/src/gpio_intr.sv \ $script_dir/../../verilog/rtl/pinmux/src/pwm.sv \ $script_dir/../../verilog/rtl/pinmux/src/timer.sv \ $script_dir/../../verilog/rtl/lib/pulse_gen_type1.sv \ $script_dir/../../verilog/rtl/lib/pulse_gen_type2.sv \ $script_dir/../../verilog/rtl/lib/registers.v \ $script_dir/../../verilog/rtl/lib/ctech_cells.sv \ 

$script_dir/../../verilog/rtl/lib/reset_sync.sv      \
$script_dir/../../verilog/rtl/qspim/src/qspim_top.sv \
$script_dir/../../verilog/rtl/qspim/src/qspim_if.sv \
$script_dir/../../verilog/rtl/qspim/src/qspim_regs.sv \
$script_dir/../../verilog/rtl/qspim/src/qspim_fifo.sv \
$script_dir/../../verilog/rtl/qspim/src/qspim_clkgen.sv \
$script_dir/../../verilog/rtl/qspim/src/qspim_ctrl.sv \
$script_dir/../../verilog/rtl/qspim/src/qspim_rx.sv \
$script_dir/../../verilog/rtl/qspim/src/qspim_tx.sv \

$script_dir/../../verilog/rtl/uart/src/uart_core.sv  \
$script_dir/../../verilog/rtl/uart/src/uart_cfg.sv   \
$script_dir/../../verilog/rtl/uart/src/uart_rxfsm.sv \
$script_dir/../../verilog/rtl/uart/src/uart_txfsm.sv \
$script_dir/../../verilog/rtl/lib/async_wb.sv   \
$script_dir/../../verilog/rtl/lib/async_fifo.sv      \
$script_dir/../../verilog/rtl/lib/async_fifo_th.sv   \
$script_dir/../../verilog/rtl/lib/double_sync_low.v  \
$script_dir/../../verilog/rtl/lib/clk_ctl.v          \
$script_dir/../../verilog/rtl/i2cm/src/core/i2cm_bit_ctrl.v      \
$script_dir/../../verilog/rtl/i2cm/src/core/i2cm_byte_ctrl.v     \
$script_dir/../../verilog/rtl/i2cm/src/core/i2cm_top.v           \
$script_dir/../../verilog/rtl/usb1_host/src/core/usbh_core.sv    \
$script_dir/../../verilog/rtl/usb1_host/src/core/usbh_crc16.sv   \
$script_dir/../../verilog/rtl/usb1_host/src/core/usbh_crc5.sv    \
$script_dir/../../verilog/rtl/usb1_host/src/core/usbh_fifo.sv    \  
$script_dir/../../verilog/rtl/usb1_host/src/core/usbh_sie.sv     \
$script_dir/../../verilog/rtl/usb1_host/src/phy/usb_fs_phy.v     \
$script_dir/../../verilog/rtl/usb1_host/src/phy/usb_transceiver.v\
$script_dir/../../verilog/rtl/usb1_host/src/top/usb1_host.sv     \
$script_dir/../../verilog/rtl/sspim/src/sspim_top.sv             \
$script_dir/../../verilog/rtl/sspim/src/sspim_ctl.sv             \
$script_dir/../../verilog/rtl/sspim/src/sspim_if.sv              \
$script_dir/../../verilog/rtl/sspim/src/sspim_cfg.sv             \
$script_dir/../../verilog/rtl/uart_i2c_usb_spi/src/uart_i2c_usb_spi.sv\

$script_dir/../../verilog/rtl/wb_host/src/wb_host.sv \
$script_dir/../../verilog/rtl/lib/async_reg_bus.sv   \
$script_dir/../../verilog/rtl/wb_interconnect/src/wb_arb.sv     \
$script_dir/../../verilog/rtl/uart2wb/src/uart2wb.sv \
$script_dir/../../verilog/rtl/uart2wb/src/uart2_core.sv \
$script_dir/../../verilog/rtl/uart2wb/src/uart_msg_handler.v \

$script_dir/../../verilog/rtl/lib/sync_wbb.sv                \
$script_dir/../../verilog/rtl/lib/sync_fifo2.sv                \
$script_dir/../../verilog/rtl/wb_interconnect/src/wb_slave_port.sv  \
$script_dir/../../verilog/rtl/wb_interconnect/src/wb_interconnect.sv  \

$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_top.sv           \
$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/ycr_core_top.sv                    \
$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/ycr_dm.sv                          \
$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/ycr_tapc_synchronizer.sv           \
$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/ycr_clk_ctrl.sv                    \
$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/ycr_scu.sv                         \
$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/ycr_tapc.sv                        \
$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/ycr_tapc_shift_reg.sv              \
$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/ycr_dmi.sv                         \
$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/primitives/ycr_reset_cells.sv      \
$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_ifu.sv           \
$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_idu.sv           \
$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_exu.sv           \
$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_mprf.sv          \
$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_csr.sv           \
$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_ialu.sv          \
$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_mul.sv           \
$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_div.sv           \
$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_lsu.sv           \
$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_hdu.sv           \
$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_tdu.sv           \
$script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr_ipic.sv               \
    $script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr_req_retiming.sv               \

$script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr_iconnect.sv                  \
$script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr_cross_bar.sv                 \
$script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr_router.sv                    \
$script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr_dmem_router.sv                \
$script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr_sram_mux.sv                   \
$script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr_tcm.sv                        \
$script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr_timer.sv                      \
    $script_dir/../../verilog/rtl/yifive/ycr1c/src/lib/ycr_arb.sv                     \

    $script_dir/../../verilog/rtl/yifive/ycr1c/src/cache/src/core/dcache_top.sv            \
    $script_dir/../../verilog/rtl/yifive/ycr1c/src/cache/src/core/dcache_tag_fifo.sv       \
    $script_dir/../../verilog/rtl/yifive/ycr1c/src/cache/src/core/icache_tag_fifo.sv       \
    $script_dir/../../verilog/rtl/yifive/ycr1c/src/cache/src/core/icache_top.sv            \
    $script_dir/../../verilog/rtl/yifive/ycr1c/src/cache/src/core/icache_app_fsm.sv        \
    $script_dir/../../verilog/rtl/yifive/ycr1c/src/lib/ycr_async_wbb.sv                    \
$script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr_dmem_wb.sv                      \
$script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr_intf.sv                        \
$script_dir/../../verilog/rtl/digital_pll/src/digital_pll_controller.v  \
$script_dir/../../verilog/rtl/digital_pll/src/digital_pll.v             \
$script_dir/../../verilog/rtl/digital_pll/src/ring_osc2x13.v    \
"

Black-box verilog and views

set ::env(VERILOG_FILES_BLACKBOX) "\ $::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/verilog/sky130_sram_2kbyte_1rw1r_32x512_8.v \ "

set ::env(EXTRA_LEFS) "\ $::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lef/sky130_sram_2kbyte_1rw1r_32x512_8.lef \ " set ::env(EXTRA_GDS_FILES) "\ $::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/gds/sky130_sram_2kbyte_1rw1r_32x512_8.gds \ "

Clock configurations

set ::env(CLOCK_PORT) "user_clock2 wb_clk_i" set ::env(CLOCK_PERIOD) "10"

set ::env(SYNTH_MAX_FANOUT) 4

CTS BUFFER

set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hdclkbuf_4 sky130_fd_sc_hdclkbuf_8 sky130_fd_sc_hd__clkbuf_16 " set ::env(CTS_SINK_CLUSTERING_SIZE) "\ 16 \ 50 \ " set ::env(CLOCK_BUFFER_FANOUT) "\ 8 \ 20 \ " set ::env(LEC_ENABLE) 0

set ::env(VERILOG_INCLUDE_DIRS) "\ [glob $script_dir/../../verilog/rtl/yifive/ycr1c/src/includes ] \ [glob $script_dir/../../verilog/rtl/i2cm/src/includes $script_dir/../../verilog/rtl/usb1_host/src/includes ] \ [glob $script_dir/../../verilog/rtl/yifive/ycr1c/src/includes ] \ [glob $script_dir/../../verilog/rtl/yifive/ycr1c/src/includes ] \ [glob $proj_dir/../../verilog/rtl/yifive/ycr1c/src/includes ] " set ::env(SYNTH_READ_BLACKBOX_LIB) 1 set ::env(SYNTH_DEFINES) [list SYNTHESIS ]

set ::env(SDC_FILE) "\
$script_dir/base.sdc \ $script_dir/pinmux.sdc \ $script_dir/qspim.sdc \ $script_dir/uart_i2cm_usb_spi_top.sdc \ $script_dir/wb_host.sdc \ $script_dir/wb_interconnect.sdc \ $script_dir/ycr_core_top.sdc \ $script_dir/ycr_iconnect.sdc \ $script_dir/ycr_intf.sdc \ " set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"

set ::env(VDD_PIN) [list {vccd1}] set ::env(GND_PIN) [list {vssd1}]

set ::env(VDD_NETS) {vccd1 vccd2 vdda1 vdda2} set ::env(GND_NETS) {vssd1 vssd2 vssa1 vssa2}

Floorplan

set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg set ::env(FP_SZING) absolute

set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro.cfg set ::env(PL_TARGET_DENSITY) 0.4 set ::env(PDN_CFG) $proj_dir/pdn_cfg.tcl

set ::env(RT_MAX_LAYER) {met5}

set ::env(FP_PDN_CHECK_NODES) 0

set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10 set ::env(DIODE_INSERTION_STRATEGY) 3

set ::env(QUIT_ON_TIMING_VIOLATIONS) "0" set ::env(QUIT_ON_MAGIC_DRC) "1" set ::env(QUIT_ON_LVS_ERROR) "1" set ::env(QUIT_ON_SLEW_VIOLATIONS) "0"

Need to cross-check why global timing opimization creating setup vio with hugh hold fix

set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) "0"

# set ::env(RUN_CVC) 0

# set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 1 set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0

Macro PDN Connections

set ::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS) "1"

set ::env(GLB_RT_OBS) " \ li1 150 130 833.1 546.54,\ met1 150 130 833.1 546.54,\ met2 150 130 833.1 546.54,\ met3 150 130 833.1 546.54,\ li1 950 130 1633.1 546.54,\ met1 950 130 1633.1 546.54,\ met2 950 130 1633.1 546.54,\ met3 950 130 1633.1 546.54,\ li1 150 750 833.1 1166.54,\ met1 150 750 833.1 1166.54,\ met2 150 750 833.1 1166.54,\ met3 150 750 833.1 1166.54,\ met5 0 0 2920 3520"

set ::env(FP_PDN_POWER_STRAPS) "vccd1 vssd1 1, vccd2 vssd2 0, vdda1 vssa1 0, vdda2 vssa2 0"

PDN offset and pitch

set ::env(FP_IO_VEXTEND) 4 set ::env(FP_IO_HEXTEND) 4

set ::env(FP_PDN_VPITCH) 100 set ::env(FP_PDN_HPITCH) 100 set ::env(FP_PDN_VWIDTH) 5 set ::env(FP_PDN_HWIDTH) 5

set ::env(FP_PDN_VOFFSET) "5" set ::env(FP_PDN_HOFFSET) "10"

set ::env(FP_PDN_HORIZONTAL_HALO) "10" set ::env(FP_PDN_VERTICAL_HALO) "10"

set ::env(FP_PDN_VSPACING) "15.5" set ::env(FP_PDN_HSPACING) "10"

pengpeng-lian commented 2 years ago

##########################Supplementary macro.cfg########################### u_dcache_2kb 150 130 N u_icache_2kb 950 130 N u_tsram0_2kb 150 750 N

pengpeng-lian commented 2 years ago

I checked the def and found the cells overlapped!

dineshannayya commented 2 years ago

I am not tried flat design in openlane flow. You need to raise issue in openroad/openlane forum.