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dineshannayya / riscduino

Arduino compatible Risc-V Based SOC
Apache License 2.0
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access latency about the sky130_sram? #18

Closed clp510 closed 2 years ago

clp510 commented 2 years ago

From the waveform I see there are 2 access latency when reading the sky130_sram, can I have 1 clock latency sky130 sram?

dineshannayya commented 2 years ago

Typically Memory will register the address for one cycle and data will be available in next cycle only. Currently only Limited version of SRAM released for tape-out. You can check with OpenRam team if they have any plan for this. [https://github.com/VLSIDA/OpenRAM]

clp510 commented 2 years ago

OK，thanks a lot