dineshannayya
commented
2 years ago Q1.: Is there a relevant FPGA test routine for the riscduino SOC? Riscduino is currently planned for Efabless MPW 130nm Skywater Free shuttle. Since complete RTL source code is available in the database, any one can port it to FPGA. Q2: There are some differences between the memory map of riscduino SOC and the memory map of caravel SOC. For example, 0x1000_0000 is QSPI config reg for riscduino and flash spi for caravel, what is the reason for this?
Riscduno has it's own RISC-V processor and it uses QSPI to boot it's processor and has it's own address mapping.
Where as caravel top-level has it's own RISC-V core which uses SPI to boot and has there own address map.
RISCDUNIO just uses Top-level RISC-V core to just boot the user core and rest of functionality is managed by RISCDUINO core.
Caravel RISC-V core can access the RISCDUNIO core through a indirect address map (As User project address space is allocated is small)
The riscduino is a great project, but after learning about it, I still have some confusion.
Is there a relevant FPGA test routine for the riscduino SOC? There are some differences between the memory map of riscduino SOC and the memory map of caravel SOC. For example, 0x1000_0000 is QSPI config reg for riscduino and flash spi for caravel, what is the reason for this?