dineshannayya
commented
2 years ago Q1. Is the Uart Master in the diagram a new addition to the RISCDUINO core? Seems like it‘s another uart input directly connected to the package pin.
A. Yes we have additional UART i/f , this has specialized Message handler though which user can configure full Riscdunio device include flashing the SPI Flash. UART message handler support messages like
Write command: wm <32 bit address> <32 bit write data>
Read command: rm <32 bit address> <32 bit read data>
We have added this additional interface incase Caravel Management WB has some issue. Here is some block diagram of WB_HOST
Q2. Actually we are planning to build a new project based on the RISCDUINO for open-mpw flow, but we have found that the memory mapping of the caravel soc and the riscduino soc are not the same. What is the basis for this? If we change the memory mapping of riscduino to match the caravel soc, what needs to be changed? A. Not sure why you need to change the address map to match with caravel.. Caravel have give a small address range 0x3000_0000 to 0x3010_000 for user project wrapper. This small address is not good enough to fit all memory space requirement for RISCDUINO. We have implemented a indirect address mapping inside the wbhost to map the caravel address to Riscduino address : assign wb_adr_int = {cfg_bank_sel[15:3],wb_adr_i[18:0]}; where cfg_bank_sel is a internal register of wb_host and this need to configure before access the Riscduino internal block. https://github.com/dineshannayya/riscduino/blob/b7535a7bee081cdb7c3da93b1191e849242740af/verilog/rtl/wb_host/src/wb_host.sv#L495
Yuxiang-Davion
Is the Uart Master in the diagram a new addition to the RISCDUINO core? Seems like it‘s another uart input directly connected to the package pin. Actually we are planning to build a new project based on the RISCDUINO for open-mpw flow, but we have found that the memory mapping of the caravel soc and the riscduino soc are not the same. What is the basis for this? If we change the memory mapping of riscduino to match the caravel soc, what needs to be changed?
BRs Yuxiang