During synthesis the following warning appears 100 times and is then suppressed (which may mean that other entities are also affected by this!):
WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'algo/uGMT/assign_iso/gen_idx_bits/brl_index_bits/phi_idx_bits/convert_coords_to_index_bits[9].phi_idx_bits_mem/phi_idx_bits_mem/ram_reg' of type 'RAMB36E1' is 'VIRTEX6'; it is being changed to match the current FPGA architecture, '7SERIES'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist or constraint file.
WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'algo/uGMT/assign_iso/gen_idx_bits/fwd_index_bits/eta_idx_bits/convert_coords_to_index_bits[0].eta_idx_bits_mem/eta_idx_bits_mem/ram_reg' of type 'RAMB36E1' is 'VIRTEX6'; it is being changed to match the current FPGA architecture, '7SERIES'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist or constraint file.
This should be fixed to make the simulation match the firmware exactly.
During synthesis the following warning appears 100 times and is then suppressed (which may mean that other entities are also affected by this!):
This should be fixed to make the simulation match the firmware exactly.