Fix broken timing

[dinyar]

Due to changes introduced in #344 timing doesn't close anymore. Resolving #205 improved things, but further changes are necessary.

[dinyar]

Current status: Duplicated output muons and index bits which seems to improve timing. Also moved to Vivado 2016.1 which helps additionally. Using phys_opt_design -directive AggressiveExplore the timing closes, however the bitfile still needs to be tested.

Also will need to adapt serializer testbench to multiplied muons and index bits.

Next steps:

• Try with updated area constraints
• Reduce size of EMTF cancel-out LUTs (they do not need the eta fine bit)
  • Can be done transparently without changing emulator etc.
• Duplicate iso bits too (need to multiply number of LUTs by factor 8, but should be no problem as they are fairly small)

[dinyar]

Current status:

• Used region-based reset signals for serializers (now possible due to refactoring from #205)
• Fixed spurious valid bit at beginning of transmission (bug introduced in previous commits to fix timing)
• Set unused output channels to transmit valid '0'
• Modified area constraints to apply only to serializers for intermediate muons. The iso bits for the final muons are on the edge wrt timing, so Vivado does a better job when it isn't constrained.

[dinyar]

Remaining issues:

• Suspicion: New reset signal seems to be in 240 MHz domain, but we need it at 40 MHz
• Valid bits for unused channel should be synched to the other valid bits (needed for verification software)

[dinyar]

Timing closes with the current HEAD.