dirkwhoffmann
commented
3 years ago it isn't possible to emulate a single clock cycle, let alone half a clock cycle.
No, this is not possible. The goal of the CPU implementation is to provide a high-speed CPU that is accurate enough for being used in an Amiga emulator or similar projects. It is cycle-accurate in the sense that the CPU issues several sync() calls during the execution of a single instruction (there is a sync() call before every memory access). Inside the sync handler, the environment (e.g., my virtual Amiga) has the ability to update the bus value w.r.t. to the current CPU cycle before the read access is carried out. This approach is perfectly suited for emulating an Amiga. It is not accurate enough for applications that require a true cycle-by-cycle execution which seems to be the case in your project.
jotego
Hello,
Although this emulator claims to be cycle-accurate, it isn't possible to emulate a single clock cycle, let alone half a clock cycle.
For accurately representing bus transactions, it would be needed to emulate the rise and falling edges of the clock. For instance, the /DTACK bus signal may take many clock cycles to come down. Maybe you have a way around that at the moment by setting the clock cycle count via a method. The important thing is that data is not in the bus when the read16 method is called, and that's why /DTACK halts the CPU, but the read16 method cannot emulate that because it has to reply with a value.
I understand that this probably falls out of your scope, but I just wanted to share it; in case you want to aim for a more truly cycle-accurate emulation.
Thank you