The current sequencer cannot handle the case that bitplane DMA is switched off in the middle of a scanline (i.e., while bitplane DMA is active). To address this scenario, the sequencer should be improved as follows:
Emulate the bpstopreq and the stop flipflop accurately.
Emulate the T-flipflop counter accurately.
Right now, when BPRUN equals 0, the counter equals 0 in my emulation. This is inaccurate because the LSB (cnt0) is represented by the HI line. Hence, if BPRUN equals 0, the counter still toggles between 0 and 1 in the real machine. This affects timing of line last which in turn affects timing of the stop flipflop.
Furthermore, there is a bug in the real OCS Agnus (ECS is even worse). If DMA is switched off after stopreq has been asserted, the flipflop doesn't seem to get cleared any more. Hence, if DMA is switched on again in the next scanline, DMA terminates early because stopreq is still asserted. I can't see this behaviour in the available schematics.
dirkwhoffmann
commented
2 years ago
The current sequencer cannot handle the case that bitplane DMA is switched off in the middle of a scanline (i.e., while bitplane DMA is active). To address this scenario, the sequencer should be improved as follows:
bpstopreqand thestopflipflop accurately.BPRUNequals 0, the counter equals 0 in my emulation. This is inaccurate because the LSB (cnt0) is represented by theHIline. Hence, ifBPRUNequals 0, the counter still toggles between 0 and 1 in the real machine. This affects timing of linelastwhich in turn affects timing of thestopflipflop.Furthermore, there is a bug in the real OCS Agnus (ECS is even worse). If DMA is switched off after
stopreqhas been asserted, the flipflop doesn't seem to get cleared any more. Hence, if DMA is switched on again in the next scanline, DMA terminates early becausestopreqis still asserted. I can't see this behaviour in the available schematics.