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divyanshmanocha / EE2-Verilog-Lab

Imperial Second Year Digital Verilog Lab
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EX5_Simulation #3

Open divyanshmanocha opened 7 years ago

divyanshmanocha commented 7 years ago

ex5_simulation

divyanshmanocha commented 7 years ago

FMAX:

fmax

divyanshmanocha commented 7 years ago

Unconstrained paths:

unconstrained ports

divyanshmanocha commented 7 years ago

counter

divyanshmanocha commented 7 years ago

waveform