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dmolinagarcia / 74HCT6526

74HCT6526
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TIMERA/TIMERB underflows issue. #10

Closed dmolinagarcia closed 1 year ago

dmolinagarcia commented 1 year ago

From CIATEST 01.cmpold. Wheneven TIMERB is loaded (or force loaded) exactly when it overflows, real CIA seems to skip an interrupt, where 74HCT6526 doesn't. This causes NMI 51C6 to fail on the test.

This is the only value that fails.

dmolinagarcia commented 1 year ago

Looking at test results... it seems the opposite, I skip the IRQ, real CIA doesn't but... totally unsure at this point.

dmolinagarcia commented 1 year ago

image

6526 on the left, 74HCT6526 on right. When TIMERB underflows right after TB Forceload, the underflow is missed, and so is the pulse, and the interrupt.

dmolinagarcia commented 1 year ago

And...

image

Logisim does not share this behaviour. IRQ fires one cycle later, but still fires.

dmolinagarcia commented 1 year ago

Needed test!

Run the test but with different values. Verify that I'm indeed triggering the timer pulse and IRQ on the exact cycle. As IRQ is not execute until current instruction ends, I may be firing with a cycle offset and still don't see it.

As the whole test runs fine, I have the feeling I'm triggering on the exact cycle, but I want to verify it.

Then focus on how to get the underflow while reloading!

dmolinagarcia commented 1 year ago

Bite me!

image

According to logisim, TBLOAD is high during 1 cycle, but start is high for two cycles. Enough that on the next cycle, to the forceload, the interrupt is triggered. Still not 100% accurate but.. 95% closer than my current version.

I need to measure 74HCT6526 with the same values as this last test. According to logisim, there's plenty of time for the pulse to happen... it isn't even an asynchronous event, so, why am I missing it?

dmolinagarcia commented 1 year ago

What signals do I need for this test?

dmolinagarcia commented 1 year ago

I'm thinking of a reduced test that I can do with a 8ch channel.

But... I may have found a solution. Neither TBLOAD nor TBHI when not running should clear the pipeline, but they do. TBHI does not matter, as timer is not running, so pipeline is already empty, but.. TBLOAD... why!!!!

If I reset the clock pipeline with TBPULSET, and have the other reload sources reset only the LOAD ff. It may just work. Just maybe...

dmolinagarcia commented 1 year ago

I'm thinking of a reduced test that I can do with a 8ch channel.

  • PHI2
  • /CS (CIA2)
  • PB6 (TAPULSE)
  • PB7 (TBPULSE)
  • TBLOAD
  • TBPRECOUNT
  • TBSTART (Output from CREG, not the register value)

But... I may have found a solution. Neither TBLOAD nor TBHI when not running should clear the pipeline, but they do. TBHI does not matter, as timer is not running, so pipeline is already empty, but.. TBLOAD... why!!!!

If I reset the clock pipeline with TBPULSET, and have the other reload sources reset only the LOAD ff. It may just work. Just maybe...

Indeed, this seems to be case, at least on LOGISIM6526. However, as forceload does not clear the pipeline, count differs by one. I need to add a DFF to delay forceload by 1 cycle. Seems to work on LOGISIM, time to do some real testing.

dmolinagarcia commented 1 year ago

Work in progress. I am adapting B1. From it's original v0.1.0 form it's now a proper 0.1.1 and still works. Will keep upgrading it until 0.2.1

dmolinagarcia commented 1 year ago

B1 and B2 upgraded to v0.2.1. The 51C6 failure is fixed but new failures are introduced. When TA=10 and both FL=1 It seems TB underflows earlier than expected. Should this be fixable, a fix will be introduced in 0.2.1 again.

Further testing required.

dmolinagarcia commented 1 year ago

A wrongfully cut trace (And one that was supposed to be cut, intact) were the cause of this. Once this has been fixed, 01cmpold success.

This fix will be incorporated in v0.2.1