about PLL and buffer ram in camera_vga_display_top module

[xselimtr]

Hello, I am a freshman at Bilkent University, and I'll use your code for my Digital Design courses' term project. I first converted all codes into VHDL, yet I had an issue. You declared clock_PLL_100_50_25MHz_inst and buffer_RAM_12x131072_inst in the camera_vga_display_top module, yet you haven't included their codes. I've searched for their code online but couldn't find anything useful. Can you please assist me with these? Regards

[xselimtr]

The corresponding code part can be found in the following:

clock_PLL_100_50_25MHz_inst : entity work.clock_PLL_100_50_25MHz
        port map (
            clk_out1 => clk_100mhz,
            clk_out2 => clk_50mhz,
            clk_out3 => clk_25mhz,  
            resetn => reset, -- assuming resetn is the same as reset
            locked => locked,
            clk_in1 => clk
        );

buffer_RAM_12x131072_inst : entity work.buffer_RAM_12x131072
        port map (
            clka => clk_50mhz,
            wea => wea,
            addra => save_address,
            dina => RGB_444_data,
            clkb => clk_50mhz,
            addrb => read_address,
            doutb => doutb
        );