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doonny / PipeCNN

An OpenCL-based FPGA Accelerator for Convolutional Neural Networks
Apache License 2.0
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RTL synthesize BUG about DSP and LUT #131

Open tommygyl opened 4 years ago

tommygyl commented 4 years ago

Dear Mr.Wang， Why when I synthesize RTL（VerilogHDL）, multiplication cannot be realized by DSP but by LUT? If I change the MAC in pipeCNN by (mulitiply operation) in OpenCL, DSPs will be synthesized. My guess is that the compiler cannot recognize the operation in Verilog, how can I correct this error？ Thank you!

doonny commented 4 years ago

How do you find that DSP is synthesized into LUTs ?

tommygyl commented 4 years ago

Sorry, it is logic utilization not LUTs. When I synthesize the pipeCNN, the DSPs usage is only 3％. board：Intel® Programmable Acceleration Card with Intel® Arria® 10 FPGA GX SDK：Intel FPGA SDK for OpenCL 17.1 图片1

tommygyl commented 4 years ago

I changed the RTL logic by simple multiply operation. It still could not use DSPs.

doonny commented 4 years ago

Please check the resource utilization in the aocx file. This report is not accurate since we did not specific the DSP usage of the RTL module in the rtl.html file

tommygyl commented 4 years ago

I understand what you mean, but how can we get resource utilization with aocx file? It seems that aocx can't be opened by any software.

sergio14890 commented 4 years ago

Hey tommy and doonny! I have a de1soc and I would like to try pipeCNN because I think it's spectacular! Can you tell me what procedures should I do? I honestly didn't get it very well. If someone could send me 1 contact I would love it

doonny commented 4 years ago

Any text editor can open the aocx file

sergio14890 commented 4 years ago

Tommygyl How did you manage to use pypeCNN one bsp17.1?